公开(公告)号：US20080191213A1

公开(公告)日：2008-08-14

申请号：US11932314

申请日：2007-10-31

申请人： Yang Ho Bae ,  Chang Oh Jeong ,  Byeong Beom Kim

发明人： Yang Ho Bae ,  Chang Oh Jeong ,  Byeong Beom Kim

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/458 ,  H01L27/124

摘要： A thin film transistor showing desirable contact characteristics during contact with indium tin oxide (ITO) or indium zinc oxide (IZO), in which a first conductive pattern including a gate electrode and a second conductive pattern including a source electrode and a drain electrode are formed without an etching process, a TFT substrate including the TFTs, and a method of manufacturing the same. The thin film transistor includes a gate electrode formed of a first conductive layer, a gate insulating layer covering the gate electrode, a semiconductor layer forming a channel on the gate insulating layer; an ohmic contact layer formed on the semiconductor layer, and a source electrode and a drain electrode formed of a second conductive layer and of a third conductive layer. The second conductive layer includes an aluminum-nickel alloy and nitrogen and is formed on the semiconductor layer. The third conductive layer includes an aluminum-nickel alloy and is formed on the second conductive layer.

摘要翻译： 在与铟锡氧化物（ITO）或铟锌氧化物（IZO）接触期间显示出期望的接触特性的薄膜晶体管，其中形成包括栅电极的第一导电图案和包括源电极和漏电极的第二导电图案 没有蚀刻处理，包括TFT的TFT基板及其制造方法。 薄膜晶体管包括由第一导电层形成的栅电极，覆盖栅电极的栅极绝缘层，在栅极绝缘层上形成沟道的半导体层; 形成在半导体层上的欧姆接触层，以及由第二导电层和第三导电层形成的源电极和漏电极。 第二导电层包括铝 - 镍合金和氮，并形成在半导体层上。 第三导电层包括铝镍合金，并形成在第二导电层上。

公开(公告)号：US09601520B2

公开(公告)日：2017-03-21

申请号：US13597940

申请日：2012-08-29

申请人： Joon Yong Park ,  Chang Oh Jeong ,  Byeong Beom Kim ,  Hong Long Ning ,  Hyung Jun Kim ,  Sang Won Shin

发明人： Joon Yong Park ,  Chang Oh Jeong ,  Byeong Beom Kim ,  Hong Long Ning ,  Hyung Jun Kim ,  Sang Won Shin

IPC分类号： H01L27/12 ,  H01L29/45 ,  G02F1/1345

CPC分类号： H01L27/124 ,  G02F1/13458 ,  G02F2202/16 ,  H01L29/458

摘要： Exemplary embodiments of the present invention relate to a panel and a display device including the same, the panel including a substrate, a signal line arranged on the substrate, the signal line configured to transmit a driving signal, an insulating layer arranged on the signal line, and a pixel electrode and a contact assistant arranged on the insulating layer. The contact assistant is electrically connected to a portion of the signal line, the contact assistant includes indium zinc oxide doped with a metal oxide not including indium or zinc, and the metal oxide has a smaller Gibbs free energy than zinc oxide.

公开(公告)号：US07276732B2

公开(公告)日：2007-10-02

申请号：US11234470

申请日：2005-09-23

申请人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

摘要翻译： 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。

公开(公告)号：US07524706B2

公开(公告)日：2009-04-28

申请号：US11844597

申请日：2007-08-24

申请人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom Seok Cho ,  Chang Oh Jeong

IPC分类号： H01L21/00

CPC分类号： H01L29/458 ,  G02F1/1368 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.

摘要翻译： 薄膜晶体管阵列面板包括由Mo合金层和Cu层构成的源电极和漏电极，Mo合金层的合金元素形成氮化物层作为对Cu层的扩散阻挡层。 可以在Mo合金层和Cu层之间，Mo合金层和半导体层之间或Mo合金层中形成氮化物层。 制造薄膜晶体管阵列面板的方法包括：形成具有第一导电层和第二导电层的数据线，所述第一导电层含有Mo合金，所述第二导电层含有Cu，并进行氮处理，使得 第一导电层中的合金元素形成氮化物层。 在形成第一导电层之前，在形成第一导电层之后，或者在形成第一导电层期间，可以进行氮处理。

公开(公告)号：US07915650B2

公开(公告)日：2011-03-29

申请号：US11930502

申请日：2007-10-31

申请人： Je Hun Lee ,  Do Hyun Kim ,  Eun Guk Lee ,  Chang Oh Jeong

发明人： Je Hun Lee ,  Do Hyun Kim ,  Eun Guk Lee ,  Chang Oh Jeong

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288

摘要： A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

摘要翻译： 薄膜晶体管包括半导体图案，源极和漏极以及栅极，半导体图案形成在基底基板上，半导体图案包括金属氧化物。 源极和漏极形成在半导体图案上，使得源极和漏极彼此间隔开，并且源极和漏极的轮廓与半导体图案的轮廓基本相同。 栅电极设置在源电极和漏电极之间的区域中，使得栅电极的一部分与源电极和漏电极重叠。 因此，由光引起的漏电流最小化。 结果，增强了薄膜晶体管的特性，减少了后图像以提高显示质量，并且提高了制造工艺的稳定性。