公开(公告)号：US08482064B2

公开(公告)日：2013-07-09

申请号：US13493505

申请日：2012-06-11

申请人： Yangbo Yi ,  Haisong Li ,  Qin Wang ,  Ping Tao ,  Lixin Zhang

发明人： Yangbo Yi ,  Haisong Li ,  Qin Wang ,  Ping Tao ,  Lixin Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696

摘要： A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.

摘要翻译： 硅超结VDMOSFET的终端包括也用作漏极区的重掺杂N型硅衬底; 漏极金属配置在重掺杂N型硅衬底的背表面上; 在重掺杂的N型硅衬底上设置N型硅外延层; 交替布置在N型硅外延层中形成P型硅柱和N型硅柱; 连续的氧化硅层设置在终端的硅表面的一部分上; 阻止移动离子漂移的结构（间隔布置的几个不连续的氧化硅层）设置在终端的硅表面的另一部分上。 阻止设置在终端区域中的移动离子的漂移的结构能够有效地防止移动离子的移动，并提高功率器件抵抗由移动离子引起的污染的能力。

公开(公告)号：US07557634B2

公开(公告)日：2009-07-07

申请号：US11596272

申请日：2004-10-20

申请人： Longxing Shi ,  Weifeng Sun ,  Haisong Li ,  Shengli Lu ,  Yangbo Yi

发明人： Longxing Shi ,  Weifeng Sun ,  Haisong Li ,  Shengli Lu ,  Yangbo Yi

IPC分类号： H03L5/00

CPC分类号： H03K19/0013 ,  H03K5/1515 ,  H03K17/162 ,  H03K2217/0036

摘要： The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit. The input end of the first out buffer unit is connected with the output end of the level switch stage as the input end of the out buffer stage, and the output end of the final output buffer unit is connected with another input end of the high voltage output stage as the output end of the out buffer stage.

摘要翻译： 低功耗CMOS高压驱动电路涉及一种用于输出驱动的高压驱动电路，并且在电平开关级的输出端与高电压输出级的输入端之间存在一个缓冲级，包括 高压PMOS管和高压NMOS管。 高压PMOS管的源极与电源连接，其栅电极与上电平缓冲器的输出端连接，作为电流输出缓冲器的输入端。 高压NMOS管的源极放在地，其栅电极作为第3序列信号的接收端。 高压PMOS管的漏极区域与高压NMOS管的漏极区域连接，并与低电平输出缓冲器单元的输入端连接，作为当前电平输出缓冲单元的输出端。 第一输出缓冲单元的输入端与电平开关级的输出端连接，作为输出缓冲级的输入端，最终输出缓冲单元的输出端连接高电压的另一输入端 输出级作为输出缓冲级的输出端。

公开(公告)号：US20070205820A1

公开(公告)日：2007-09-06

申请号：US11596272

申请日：2004-10-20

申请人： Longxing Shi ,  Weifeng Sun ,  Haisong Li ,  Yangbo Yi

发明人： Longxing Shi ,  Weifeng Sun ,  Haisong Li ,  Yangbo Yi

IPC分类号： H03B1/00

CPC分类号： H03K19/0013 ,  H03K5/1515 ,  H03K17/162 ,  H03K2217/0036

摘要： The low power consumption CMOS high voltage driving circuit relates to a kind of high voltage driving circuit for output driving, and there is an out buffer stage between the output end of the level switch stage and the input end of the high voltage output stage, comprising a high voltage PMOS pipe and a high voltage NMOS pipe. The source of the high voltage PMOS pipe is connected with the power supply, its gate electrode is connected with the output end of the upper level out buffer unit as the input end of the current level out buffer unit. The source of the high voltage NMOS pipe is put to earth, and its gate electrode serves as the receiving end of the 3ith sequence signal. The drain region of the high voltage PMOS pipe is connected with that of the high voltage NMOS pipe and is connected with the input end of the lower level out buffer unit as the output end of the current level out buffer unit. The input end of the first out buffer unit is connected with the output end of the level switch stage as the input end of the out buffer stage, and the output end of the final output buffer unit is connected with another input end of the high voltage output stage as the output end of the out buffer stage.

摘要翻译： 低功耗CMOS高压驱动电路涉及一种用于输出驱动的高压驱动电路，并且在电平开关级的输出端与高电压输出级的输入端之间存在一个缓冲级，包括 高压PMOS管和高压NMOS管。 高压PMOS管的源极与电源连接，其栅电极与上电平缓冲器的输出端连接，作为电流输出缓冲器的输入端。 高压NMOS管的源极放在地，其栅电极作为第3序列信号的接收端。 高压PMOS管的漏极区域与高压NMOS管的漏极区域连接，并与低电平输出缓冲器单元的输入端连接，作为当前电平输出缓冲单元的输出端。 第一输出缓冲单元的输入端与电平开关级的输出端连接，作为输出缓冲级的输入端，最终输出缓冲单元的输出端连接高电压的另一输入端 输出级作为输出缓冲级的输出端。

公开(公告)号：US11242859B2

公开(公告)日：2022-02-08

申请号：US16792898

申请日：2020-02-18

申请人： Yangbo Yi

发明人： Yangbo Yi

IPC分类号： F21V33/00 ,  F04D25/08 ,  F04D29/52 ,  F04D19/00 ,  F04D29/66 ,  F21Y115/10

摘要： A vertical lighting vaneless inverter fan comprises a body, a blast system, an air supply column, a lighting device and a sound-reducing structure. The blast system is mounted in the inner chamber of body. The air supply column is installed on the top of body. The blast system supplies air to the air supply column, the airflow is jetted from the air supply column. The impeller is located above the motor. When the blast system is installed in the inner chamber of body case, the impeller corresponds to the bottom of air outlet, so that the wind can be delivered through the air outlet directly.