公开(公告)号：US20110038208A1

公开(公告)日：2011-02-17

申请号：US12914020

申请日：2010-10-28

申请人： Yao-Wen CHANG ,  Tao-Cheng Lu

发明人： Yao-Wen CHANG ,  Tao-Cheng Lu

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US20120243334A1

公开(公告)日：2012-09-27

申请号：US13069778

申请日：2011-03-23

申请人： Hsing-Wen CHANG ,  Yao-Wen CHANG ,  Chu-Yung LIU

发明人： Hsing-Wen CHANG ,  Yao-Wen CHANG ,  Chu-Yung LIU

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/3418

摘要： A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M−1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是正整数。 存储器阵列包括多个存储单元，并且电连接到多个字线和多个位线。 行解码器在使能期间驱动字线中的特定字线。 M页缓冲器将使能周期划分为N个子周期，其中N是大于2的整数。此外，第i，（i + N）th，（i + 2N）th。 。 。 在第i个子周期期间，由M页缓冲器驱动（i +（M-1）×N）位线，以便对与特定字线电连接的存储单元进行编程，其中i是整数，1＆nlE ; i＆nlE; N。