公开(公告)号：US08605507B2

公开(公告)日：2013-12-10

申请号：US13349130

申请日：2012-01-12

申请人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

发明人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.

摘要翻译： 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为通过在第一条件下偏置位线和串选择线来产生编程偏置脉冲; 当位线和串选择线处于第一状态时，将耦合到目标单元的字线设置为第一电压电平; 此后，将位线和串选择线偏置在第二状态中; 以及当位线和串选择线处于第二状态时，将耦合到目标单元的字线设置为高于第一电压电平的第二电压电平。 以这种方式产生的编程偏置脉冲可以用于调制增量阶梯式脉冲编程序列。

公开(公告)号：US08004890B2

公开(公告)日：2011-08-23

申请号：US12437826

申请日：2009-05-08

申请人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

发明人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C11/56 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.

摘要翻译： 用于降低非易失性存储器中的第二位效应的非易失性存储器的操作方法适合于具有第一存储位置和第二存储位置的N级存储器单元（其中N是大于 2）。 该方法包括以下步骤：根据第二存储位置的水平确定用于操作第一存储位置的操作级别集合; 当第二存储位置的电平为较低电平时，根据第一组操作电平操作第一存储位置; 当第二存储位置的电平为较高电平时，根据第二组操作电平来操作第一存储位置。 第二组操作级别中的每个级别都大于第一组操作级别中的相应级别。

公开(公告)号：US20100284220A1

公开(公告)日：2010-11-11

申请号：US12437826

申请日：2009-05-08

申请人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

发明人： Yao-Wen Chang ,  Tao-Cheng Lu ,  I-Chen Yang ,  Hsing-Wen Chang

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0475 ,  G11C11/56 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634

摘要： An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.

摘要翻译： 用于降低非易失性存储器中的第二位效应的非易失性存储器的操作方法适用于具有第一存储位置和第二存储位置的N级存储器单元（其中N是大于 2）。 该方法包括以下步骤：根据第二存储位置的水平确定用于操作第一存储位置的操作级别集合; 当第二存储位置的电平为较低电平时，根据第一组操作电平操作第一存储位置; 当第二存储位置的电平为较高电平时，根据第二组操作电平来操作第一存储位置。 第二组操作级别中的每个级别都大于第一组操作级别中的相应级别。

公开(公告)号：US07486086B2

公开(公告)日：2009-02-03

申请号：US11979576

申请日：2007-11-06

申请人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hsing-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R27/26

CPC分类号： G01R31/2621

摘要： A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

摘要翻译： 提供了一种用于测量MOS器件的本征电容的方法。 MOS器件包括第一端子，第二端子，第三端子和第四端子。 首先，向第二终端提供第一输入信号，并将第三终端和第四终端接地。 然后，对第一终端充电并测量对第一终端充电所需的第一电流。 然后，向第二终端提供第二输入信号，将第三端子和第四端子接地，并测量对第一端子充电所需的第二电流，其中第一输入信号和第二输入信号具有相同的低电平，但是 不同的高层次。 最后，根据第一电流，第二电流和第一输入信号与第二输入信号之间的高电平差来确定第一端子和第二端子之间的本征电容。

公开(公告)号：US5311857A

公开(公告)日：1994-05-17

申请号：US900200

申请日：1992-06-17

申请人： Hsing-Wen Chang

发明人： Hsing-Wen Chang

IPC分类号： F04D25/16 ,  F04D29/62 ,  F04D29/70 ,  F24C15/20

CPC分类号： F04D25/166 ,  F04D29/626 ,  F04D29/703

摘要： A smoke exhauster structure comprises an enclosure having a releasably secured lower hood plate and a releasably secured fan housing disposed therein. The hood plate has a pair of spring loaded pivoting catches provided on respective rear corner portions thereof and a pair of protruding tabs on the front edge thereof which overlap and abut a retaining rim provided under the front panel of the enclosure. Each pivoting catch engages a respective locking bar in a rear portion of the enclosure to releasably secure the hood thereunder. The fan housing which surrounds the exhaust fans of the exhauster is releasably secured to the underside of a top plate of the enclosure by a set of latches provided around the periphery thereof. Each latch has a pivoting buckle whose ends are connected to a spring loaded lever, each buckle engages a corresponding hook shaped securing appendage provided on the underside of the top plate.

摘要翻译： 抽烟器结构包括具有可释放地固定的下罩板和设置在其中的可释放地固定的风扇壳体的外壳。 发动机罩板具有设置在其相应的后角部上的一对弹簧加载的枢转卡爪和在其前边缘上的一对突出突片，其与设置在外壳的前面板下方的保持边缘重叠并邻接。 每个枢转卡扣与壳体的后部中的相应的锁定杆接合以可释放地固定其下的罩。 围绕排气扇的排风扇的风扇壳体通过围绕其周边设置的一组闩锁可释放地固定到外壳的顶板的下侧。 每个闩锁具有枢转带扣，其端部连接到弹簧加载的杠杆，每个扣环接合设置在顶板的下侧上的相应的钩状固定附件。

公开(公告)号：US08644081B2

公开(公告)日：2014-02-04

申请号：US13069778

申请日：2011-03-23

申请人： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chu-Yung Liu

发明人： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chu-Yung Liu

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/3418

摘要： A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M−1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是正整数。 存储器阵列包括多个存储单元，并且电连接到多个字线和多个位线。 行解码器在使能期间驱动字线中的特定字线。 M页缓冲器将使能周期划分为N个子周期，其中N是大于2的整数。此外，第i，（i + N）th，（i + 2N）th。 。 。 ，在第i个子周期期间，由M页缓冲器驱动（i +（M-1）* N）位线，以便对与特定字线电连接的存储单元进行编程，其中i是整数和1 @在。

公开(公告)号：US5628289A

公开(公告)日：1997-05-13

申请号：US570493

申请日：1995-12-11

申请人： Hsing-Wen Chang

发明人： Hsing-Wen Chang

IPC分类号： F24C15/20

CPC分类号： F24C15/20

摘要： A smoke exhauster comprises an enclosure including a fan housing and a flood plate releasably secured thereunder. The enclosure has a plurality of spiral coupling recesses on the top plate for releasable securing the fan housing by a T-shaped fastener. The hood plate has at four corners a sliding catch member positioned in registry with the corresponding locking holes on the enclosure so as to permit the hood plate to be slidingly secured to the enclosure. The hood plate can be suspended from the rear of the enclosure if the sliding catch member on the rear is not intended to be disengaged. This arrangement provides faster and more convenient assembly or disassembly of the smoke exhauster for facilitating a rapid removal of the oil and grime accumulated on them.

摘要翻译： 抽烟器包括一个外壳，包括一个风扇外壳和一个可释放地固定在其下的防水板。 外壳在顶板上具有多个螺旋联接凹槽，用于通过T形紧固件可释放地固定风扇壳体。 发动机盖板在四个角处具有滑动卡扣构件，其被定位成与外壳上的对应的锁定孔对准，以便允许罩板滑动地固定到外壳。 如果后部的滑动卡扣构件不打算脱开，则罩板可以从外壳的后部悬挂。 这种布置提供了更快且更方便的排烟器的组装或拆卸，以便于快速除去积聚在其上的油和污垢。

公开(公告)号：US20130182505A1

公开(公告)日：2013-07-18

申请号：US13349130

申请日：2012-01-12

申请人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

发明人： Chuyung Liu ,  Hsing-Wen Chang ,  Yaowen Chang ,  Tao-Cheng Lu

IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a program bias pulse by biasing the bit lines and string select lines in a first condition; setting a word line coupled to a target cell to a first voltage level while the bit lines and string select lines are in the first condition; thereafter, biasing the bit lines and string select lines in a second condition; and setting the word line coupled to the target cell to a second voltage level higher than the first voltage level while the bit lines and string select lines are in the second condition. Program bias pulses produced in this manner can be used in a modulated incremental stepped pulse programming sequence.

摘要翻译： 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为通过在第一条件下偏置位线和串选择线来产生编程偏置脉冲; 当位线和串选择线处于第一状态时，将耦合到目标单元的字线设置为第一电压电平; 此后，将位线和串选择线偏置在第二状态中; 以及当位线和串选择线处于第二状态时，将耦合到目标单元的字线设置为高于第一电压电平的第二电压电平。 以这种方式产生的编程偏置脉冲可以用于调制增量阶梯式脉冲编程序列。

公开(公告)号：US20130027116A1

公开(公告)日：2013-01-31

申请号：US13194039

申请日：2011-07-29

申请人： Ju-An Chiang ,  Hsing-Wen Chang

发明人： Ju-An Chiang ,  Hsing-Wen Chang

IPC分类号： H01L37/00

CPC分类号： G05F3/30 ,  H01L27/0248

摘要： A temperature compensation circuit, applied on a metal oxide semiconductor (MOS) transistor, with a threshold voltage varying with respect to a temperature value of the MOS transistor, for having the MOS transistor corresponding to an equivalent threshold voltage substantially with a constant value throughout a temperature range, comprises a voltage generator. The voltage generator provides a voltage proportional to absolute temperature (VPTAT) to drive the body of the MOS transistor in such way that a variation of the threshold voltage due to temperature variation of the MOS transistor is substantially compensated with a variation of the threshold voltage due to body-source voltage variation of the MOS transistor, so that the MOS transistor corresponds to the equivalent threshold voltage that is temperature invariant.

摘要翻译： 一种温度补偿电路，其施加在金属氧化物半导体（MOS）晶体管上，阈值电压相对于MOS晶体管的温度值而变化，以使MOS晶体管对应于基本上具有恒定值的等效阈值电压 温度范围包括电压发生器。 电压发生器提供与绝对温度（VPTAT）成比例的电压，以驱动MOS晶体管的主体，使得由于MOS晶体管的温度变化导致的阈值电压的变化基本上被阈值电压的变化补偿 到MOS晶体管的体源电压变化，使得MOS晶体管对应于温度不变的等效阈值电压。

公开(公告)号：US20120243334A1

公开(公告)日：2012-09-27

申请号：US13069778

申请日：2011-03-23

申请人： Hsing-Wen CHANG ,  Yao-Wen CHANG ,  Chu-Yung LIU

发明人： Hsing-Wen CHANG ,  Yao-Wen CHANG ,  Chu-Yung LIU

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/3418

摘要： A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M−1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1≦i≦N.

摘要翻译： 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是正整数。 存储器阵列包括多个存储单元，并且电连接到多个字线和多个位线。 行解码器在使能期间驱动字线中的特定字线。 M页缓冲器将使能周期划分为N个子周期，其中N是大于2的整数。此外，第i，（i + N）th，（i + 2N）th。 。 。 在第i个子周期期间，由M页缓冲器驱动（i +（M-1）×N）位线，以便对与特定字线电连接的存储单元进行编程，其中i是整数，1＆nlE ; i＆nlE; N。