公开(公告)号：US07981735B2

公开(公告)日：2011-07-19

申请号：US12434779

申请日：2009-05-04

申请人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

发明人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC分类号： H01L21/336

CPC分类号： H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US07545000B2

公开(公告)日：2009-06-09

申请号：US11485837

申请日：2006-07-13

申请人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

发明人： Yark Yeon Kim ,  Seong Jae Lee ,  Moon Gyu Jang ,  Chel Jong Choi ,  Myung Sim Jun ,  Byoung Chul Park

IPC分类号： H01L27/01

CPC分类号： H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

摘要： Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

摘要翻译： 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道，将肖特基势垒隧道晶体管的栅极侧壁损坏所造成的漏电流减到最小 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US07713826B2

公开(公告)日：2010-05-11

申请号：US12045797

申请日：2008-03-11

申请人： Chel Jong Choi ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Myung Sim Jun ,  Tae Youb Kim

发明人： Chel Jong Choi ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Myung Sim Jun ,  Tae Youb Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.

摘要翻译： 提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。 该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。 在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

公开(公告)号：US20080299736A1

公开(公告)日：2008-12-04

申请号：US12045797

申请日：2008-03-11

申请人： Chel Jong Choi ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Myung Sim Jun ,  Tae Youb Kim

发明人： Chel Jong Choi ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Myung Sim Jun ,  Tae Youb Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28229 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.

摘要翻译： 提供一种制造包括使用界面反应形成的高k电介质薄层的半导体器件的方法。 该方法包括以下步骤：在硅衬底上形成氧化物层; 使用氧化物层和金属层之间的界面反应，在氧化物层上沉积金属层以形成金属硅酸盐层; 通过蚀刻金属硅酸盐层和金属层形成金属栅极; 以及在形成金属栅极之后在硅衬底中形成轻掺杂漏极（LDD）区域和源极和漏极区域。 在该方法中，可以通过更简单的工艺以较低的成本制造具有高品质和高性能的半导体器件。

公开(公告)号：US07605068B2

公开(公告)日：2009-10-20

申请号：US11345265

申请日：2006-01-31

申请人： Chel Jong Choi ,  Yong Jin Kim ,  Hi Deok Lee

发明人： Chel Jong Choi ,  Yong Jin Kim ,  Hi Deok Lee

IPC分类号： H01L21/3205 ,  H01L21/44

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

摘要： Provided is a semiconductor device and a manufacturing method thereof. The method includes the steps of: forming a thin film transistor including a substrate having a semiconductor layer and silicon, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, and source and drain regions formed in the semiconductor layer; forming a first metal layer on the substrate having the semiconductor layer and the gate electrode; forming a second metal layer on the first metal layer; forming a third metal layer on the second metal layer; forming a nitride layer on the third metal layer; and annealing the substrate having the nitride layer, and forming a silicide layer on the gate electrode and the source and drain regions.

摘要翻译： 提供一种半导体器件及其制造方法。 该方法包括以下步骤：形成薄膜晶体管，其包括具有半导体层和硅的衬底，形成在半导体层上的栅极绝缘层，形成在栅极绝缘层上的栅极电极以及形成在栅极绝缘层中的源极和漏极区域 半导体层; 在具有半导体层和栅电极的基板上形成第一金属层; 在所述第一金属层上形成第二金属层; 在所述第二金属层上形成第三金属层; 在所述第三金属层上形成氮化物层; 以及使具有氮化物层的衬底退火，以及在栅电极和源极和漏极区上形成硅化物层。