公开(公告)号：US5787268A

公开(公告)日：1998-07-28

申请号：US497375

申请日：1995-06-30

申请人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

发明人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5022 ,  G06F17/5045

摘要： The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

摘要翻译： 本发明提供了一种交互式电路设计装置，其中逻辑设计，布局设计和速度分析可以在处理中相互配合。 交互式电路设计装置包括用于逻辑设计设计对象电路的逻辑设计部分，布局设计部分，用于基于逻辑设计的结果执行构成设计对象电路的逻辑部件的安装布置，并且在逻辑部件之间执行布线， 以及速度分析部件，用于根据布局的结果，基于对设计对象电路中的每个路径的延迟的计算来执行速度分析。 逻辑设计部分，布局设计部分和速度分析部分彼此连接，以便在必要时相互配合。 交互式电路设计装置适用于设计LSI，印刷电路板等元件的电路的装置。

公开(公告)号：US5892685A

公开(公告)日：1999-04-06

申请号：US669766

申请日：1996-06-25

申请人： Hiroyuki Sugiyama ,  Terunobu Maruyama ,  Ryouichi Yamashita

发明人： Hiroyuki Sugiyama ,  Terunobu Maruyama ,  Ryouichi Yamashita

IPC分类号： G06F17/50 ,  G06F17/00

CPC分类号： G06F17/5068

摘要： A packaging design system for an LSI circuit includes: a gate placement preparation unit for preparing basic placement data for gates used as an original data for producting the LSI circuit; a wiring data preparation unit operatively connected to the gate placement preparation unit for preparing wiring data based on wiring patterns each having the same length between gates; a delay calculation unit operatively connected to the wiring data preparation unit for calculating net delays between gates and path delays from a clock input until an output in the LSI circuit; a standard path delay determining unit operatively connected to the delay calculation unit for determining a standard path delay in accordance with distribution of path delays; and a macro determining unit operatively connected to the standard path delay determining unit for selecting the macros in accordance with predetermined conditions of path delays, and selected several macros being used for an actual placement of gates.

摘要翻译： LSI电路的封装设计系统包括：栅极布置准备单元，用于准备用作用于产生LSI电路的原始数据的门的基本布局数据; 布线数据准备单元，其可操作地连接到所述栅极布置准备单元，用于基于栅极之间具有相同长度的布线图形来准备布线数据; 延迟计算单元，可操作地连接到所述布线数据准备单元，用于计算从时钟输入到LSI电路的输出之间的门与路径延迟之间的净延迟; 标准路径延迟确定单元，可操作地连接到所述延迟计算单元，用于根据路径延迟的分布确定标准路径延迟; 以及宏确定单元，其可操作地连接到标准路径延迟确定单元，用于根据路径延迟的预定条件选择宏，以及选择的几个宏用于门的实际放置。