公开(公告)号：US5787268A

公开(公告)日：1998-07-28

申请号：US497375

申请日：1995-06-30

申请人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

发明人： Yaroku Sugiyama ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryouichi Yamashita ,  Terunobu Maruyama ,  Yasunori Abe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5022 ,  G06F17/5045

摘要： The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

摘要翻译： 本发明提供了一种交互式电路设计装置，其中逻辑设计，布局设计和速度分析可以在处理中相互配合。 交互式电路设计装置包括用于逻辑设计设计对象电路的逻辑设计部分，布局设计部分，用于基于逻辑设计的结果执行构成设计对象电路的逻辑部件的安装布置，并且在逻辑部件之间执行布线， 以及速度分析部件，用于根据布局的结果，基于对设计对象电路中的每个路径的延迟的计算来执行速度分析。 逻辑设计部分，布局设计部分和速度分析部分彼此连接，以便在必要时相互配合。 交互式电路设计装置适用于设计LSI，印刷电路板等元件的电路的装置。

公开(公告)号：US06240541B1

公开(公告)日：2001-05-29

申请号：US09227967

申请日：1999-01-11

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制 单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US5889677A

公开(公告)日：1999-03-30

申请号：US574901

申请日：1995-12-19

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及 显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US06560763B1

公开(公告)日：2003-05-06

申请号：US09637642

申请日：2000-08-14

申请人： Hiroyuki Sugiyama ,  Yasunori Abe ,  Naomi Bizen ,  Hiroshi Ikeda

发明人： Hiroyuki Sugiyama ,  Yasunori Abe ,  Naomi Bizen ,  Hiroshi Ikeda

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： A route searching method is used for circuit design, and includes a step of setting, with respect to each pin, a corresponding flag of a pass flag which indicates that a pin is passed, a searching flag which indicates that a pin is being searched, and a branch flag which indicates that a pin is a branch point, and a step of determining a direction of a route search depending on each flag which is set with respect to each pin.

摘要翻译： 路径搜索方法用于电路设计，并且包括针对每个引脚设置指示引脚通过的通过标志的相应标志的步骤，指示正在搜索引脚的搜索标志， 以及分支标志，其指示引脚是分支点，以及根据针对每个引脚设置的每个标志来确定路线搜索的方向的步骤。

公开(公告)号：US06308305B1

公开(公告)日：2001-10-23

申请号：US08874506

申请日：1997-06-13

申请人： Hiroyuki Sugiyama ,  Yasunori Abe ,  Naomi Bizen

发明人： Hiroyuki Sugiyama ,  Yasunori Abe ,  Naomi Bizen

IPC分类号： G06F1750

CPC分类号： G06F17/5031 ,  G06F17/5068

摘要： There are disclosed a method and an apparatus for circuit designing, which enable arranging and wiring operations to be efficiently performed by using indices for arranging and wiring without the occurrence of any error paths. In the method and apparatus for circuit designing, path tracing is performed from one or more tracing start pins for a result of logical designing and the number of passing through each pin of cells to be arranged is counted during the path tracing. Thus, the method and apparatus for circuit designing are suitably used for designing of a circuit such as a LSI or the like, which has been enlarged in size and complex following an advance in a micro fabrication art.

摘要翻译： 公开了一种用于电路设计的方法和装置，其能够通过使用用于布置和布线的索引来有效地执行排列和布线操作，而不发生任何错误路径。 在用于电路设计的方法和装置中，对于逻辑设计的结果，从一个或多个跟踪起始引脚执行路径跟踪，并且在路径跟踪期间对要布置的单元的每个引脚的数量进行计数。 因此，用于电路设计的方法和装置适合用于诸如LSI等的电路的设计，其尺寸和复杂性随着微加工领域的进步而扩大。

公开(公告)号：US08779764B2

公开(公告)日：2014-07-15

申请号：US13321896

申请日：2010-07-13

申请人： Kenichi Meguro ,  Hiroyuki Hoshiya ,  Keizou Katou ,  Yasunori Abe

发明人： Kenichi Meguro ,  Hiroyuki Hoshiya ,  Keizou Katou ,  Yasunori Abe

IPC分类号： G01R33/02

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G01B7/30 ,  H01L43/08 ,  H01L43/12

摘要： To provide a method which can define the direction and orientation of magnetization of a pinned layer while reducing the number of steps of forming a GMR film. The magnetization direction of the pinned layer is defined in a plurality of directions by forming a plurality of patterns having directivities. Further, when the magneto-resistive effect film is formed, a magnetic field is applied in a direction at an angle set between the angles of the plurality of patterns.

摘要翻译： 提供一种可以限定被钉扎层的磁化方向和取向同时减少形成GMR膜的步骤数量的方法。 钉扎层的磁化方向通过形成具有方向性的多个图案而在多个方向上限定。 此外，当形成磁阻效应膜时，以在多个图案的角度之间设定的角度的方向施加磁场。

公开(公告)号：US07456758B2

公开(公告)日：2008-11-25

申请号：US11676608

申请日：2007-02-20

申请人： Hiroyuki Hoshiya ,  Kenichi Meguro ,  Kazuhiro Nakamoto ,  Yasunori Abe

发明人： Hiroyuki Hoshiya ,  Kenichi Meguro ,  Kazuhiro Nakamoto ,  Yasunori Abe

IPC分类号： H03M1/22

CPC分类号： G01D5/145 ,  B82Y25/00 ,  G01R33/093 ,  G11B5/59683

摘要： To provide a magnetic encoder having high resolution and a high output, and a magnetoresistive sensor for an encoder. A fine sensor having a reduced demagnetization field is produced by: forming a free layer consists of a laminated soft magnetic film in which two soft magnetic layers are coupled in anti-parallel, and setting the width of a sensor unit to 2 μm to 4 μm.

摘要翻译： 提供具有高分辨率和高输出的磁编码器和用于编码器的磁阻传感器。 具有减少退磁场的精细传感器通过以下方式产生：形成自由层，其由两层软磁层反平行连接的层叠软磁膜构成，并将传感器单元的宽度设定为2μm至4μm 。

公开(公告)号：US07395709B2

公开(公告)日：2008-07-08

申请号：US11457484

申请日：2006-07-14

申请人： Masaru Noda ,  Yasunori Abe

发明人： Masaru Noda ,  Yasunori Abe

IPC分类号： G01P15/08 ,  G11B21/02

CPC分类号： G01P15/18 ,  G01P15/0891

摘要： A fall detection device is provided, which accomplishes a fall judgment on acceleration by a simple calculation and improves uniformity of effective threshold value for the acceleration judgment as to a direction of an applied acceleration vector. The fall detection device produces a fall detection signal when an absolute value of each axis component of an acceleration measured by a three-axis acceleration sensor is less than a first threshold value, and when a sum of the absolute values of the axis components of the acceleration is less than a second threshold value that is 1.5 times to twice the first threshold value.

摘要翻译： 提供一种通过简单计算来实现对加速度的下降判断的下降检测装置，并且提高了对于所施加的加速度矢量的方向的加速判断的有效阈值的均匀性。 当由三轴加速度传感器测量的加速度的每个轴分量的绝对值小于第一阈值时，下降检测装置产生跌倒检测信号，并且当三轴加速度传感器的轴分量的绝对值之和 加速度小于第一阈值的1.5倍至第二阈值的两倍的第二阈值。

公开(公告)号：US20060236761A1

公开(公告)日：2006-10-26

申请号：US11356238

申请日：2006-02-17

申请人： Hideki Inoue ,  Munetoshi Unuma ,  Yasunori Abe ,  Masakatsu Saitoh

发明人： Hideki Inoue ,  Munetoshi Unuma ,  Yasunori Abe ,  Masakatsu Saitoh

IPC分类号： G01P15/00 ,  G01P15/18 ,  G01P13/00

CPC分类号： G01P3/22 ,  G01P15/0891 ,  G01P15/18 ,  G01P2015/084 ,  G11B19/04 ,  H04M2250/12

摘要： A free fall detection device capable of detecting a fall accompanied by rotation is provided. A fall accompanied by rotation is detected based on a waveform of an acceleration signal output from the acceleration detection unit and an angular velocity signal output from the angular velocity detection unit. A gravity center acceleration of the device to be protected is calculated from the acceleration detected by the acceleration detection unit and from the angular velocity detected by the angular velocity detection unit. Even when the device being protected rotates as it falls, the fall of the device can be detected from the detected acceleration or angular velocity. Further, by calculating the gravity center acceleration not affected by the rotation, it is possible to detect a fall of the device with high precision even if the device rotates as it falls.

公开(公告)号：US09250301B2

公开(公告)日：2016-02-02

申请号：US14117555

申请日：2012-08-10

申请人： Yasuyuki Okada ,  Yasunori Abe

发明人： Yasuyuki Okada ,  Yasunori Abe

IPC分类号： G01R33/09 ,  G01B7/14 ,  G01D5/245 ,  G01B7/00 ,  G01D5/244

CPC分类号： G01R33/09 ,  G01B7/003 ,  G01D5/24438 ,  G01D5/2451

摘要： A magnetic medium is magnetized in the relative movement direction at a predefined pitch km and a magnetic sensor includes plural magnetoresistive elements whose electrical resistance value changes depending on a magnetic field at a place where the magnetoresistive element is disposed. A position where the magnetoresistive element is disposed is defined as a reference position and, in addition to the magnetoresistive element of this reference position, the magnetoresistive elements as harmonic reducing patterns are disposed at the following positions, with P(n) defined as the n-th prime: a position offset by λm/(2·P(n)) from the reference position toward at least one side of the relative movement direction, wherein N≧n>1 and N is a natural number satisfying N>3, and a position further offset by λm/(2·P(L+1)) from a position offset by λm/(2·P(L)), wherein 1

摘要翻译： 磁介质以预定间距km在相对移动方向上磁化，并且磁性传感器包括多个磁阻元件，其电阻值根据设置有磁阻元件的位置处的磁场而改变。 定义磁阻元件的位置被定义为参考位置，并且除了该参考位置的磁阻元件之外，作为谐波减小图案的磁阻元件被设置在以下位置，其中P（n）被定义为n 第一素数：从基准位置朝向相对移动方向的至少一侧偏移λm/（2·P（n））的位置，其中N≥n> 1且N是满足N≥3的自然数， 以及从偏移λm/（2·P（L））的位置进一步偏移λm/（2·P（L + 1））的位置，其中1