公开(公告)号：US6105124A

公开(公告)日：2000-08-15

申请号：US672100

申请日：1996-06-27

申请人： Yaron Farber ,  Gad Sheaffer ,  Robert Valentine

发明人： Yaron Farber ,  Gad Sheaffer ,  Robert Valentine

IPC分类号： G06F9/45 ,  G06F11/34 ,  G06F11/36 ,  G06F9/30

CPC分类号： G06F8/445 ,  G06F8/52 ,  G06F11/3466 ,  G06F2201/865 ,  G06F2201/88

摘要： A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.

摘要翻译： 一种用于合并二进制转换的基本指令块的方法。 该方法用于在存储器中具有包括指令块的第一组指令的计算机系统，以及用于将可在源指令集架构上执行的指令转换为可在目标指令集架构上执行的指令的转换器。 该方法包括第一步骤，由翻译器确定从第一指令块到第二指令块的执行顺序。 该方法的第二步包括由翻译器生成代表按照执行次序在存储单元中相邻的第一和第二指令块的指令的超块。

公开(公告)号：US5903760A

公开(公告)日：1999-05-11

申请号：US669772

申请日：1996-06-27

申请人： Yaron Farber ,  Yossi Levhari ,  Leonid Baraz ,  Gallia Ladiray

发明人： Yaron Farber ,  Yossi Levhari ,  Leonid Baraz ,  Gallia Ladiray

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/45 ,  G06F9/455

CPC分类号： G06F9/30174 ,  G06F8/443 ,  G06F9/30094 ,  G06F9/3808

摘要： A method for increasing the performance of binary translated conditional instructions. According to one embodiment of the invention, a conditional instruction compatible with the first ISA is decoded. The condition of the conditional instruction is dependent on at least on status flag. The conditional instruction is translated to be compatible with a second ISA, wherein the condition of the conditional instruction is altered to be dependent on a previously computed difference between two values, the difference residing in a memory location.

摘要翻译： 一种提高二进制翻译条件指令性能的方法。 根据本发明的一个实施例，解码与第一ISA兼容的条件指令。 条件指令的条件至少取决于状态标志。 条件指令被转换为与第二ISA兼容，其中条件指令的条件被改变为依赖于先前计算的两个值之间的差异，差异驻留在存储器位置中。

公开(公告)号：US5721927A

公开(公告)日：1998-02-24

申请号：US689357

申请日：1996-08-07

申请人： Leonid Baraz ,  Yaron Farber

发明人： Leonid Baraz ,  Yaron Farber

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/45 ,  G06F9/455 ,  G06F11/28 ,  G06F9/32

CPC分类号： G06F9/3802 ,  G06F11/28 ,  G06F8/52 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/45504

摘要： A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. The compare instruction compares a first value from the first block of instructions with a second value from the second block of instructions, which precedes the first block of instructions in the order of execution. The method further includes appending a branching instruction to the first block of instructions. The branching instruction is executed in response to the first value being unequal to the second value. The branching instruction, when executed, branches to an alternative look-up routine to obtain a block of instructions that follows the second block of instructions in the order of execution.

摘要翻译： 一种用于使得第一指令块能够以执行顺序验证第一指令块是否遵循第二指令块的方法。 该方法包括将比较指令附加到第一指令块。 比较指令将来自第一指令块的第一值与来自执行顺序的第一指令块之前的第二指令块的第二值进行比较。 该方法还包括将分支指令附加到第一指令块。 响应于第一值不等于第二值来执行分支指令。 分支指令在执行时分支到另一查找例程，以按照执行顺序获得遵循第二指令块的指令块。