公开(公告)号：US20100169525A1

公开(公告)日：2010-07-01

申请号：US12377804

申请日：2006-08-23

申请人： Yaron Natanel ,  Ron Bercovich ,  Norman Goldstein ,  Ori Goren

发明人： Yaron Natanel ,  Ron Bercovich ,  Norman Goldstein ,  Ori Goren

IPC分类号： G06F13/38 ,  G06F13/00

CPC分类号： G06F13/362

摘要： A pipelined device and method for executing transactions in a pipelined device, the method includes: setting limiter thresholds that define a maximal amount of pending transaction requests to be provided from one pipeline stage to another pipeline stage; executing an application while monitoring the performance of a device that comprises pipeline limiters; wherein the executing includes: selectively transferring transaction requests from one stage of the pipeline to another in response to the limiter thresholds, arbitrating between transaction requests at a certain pipeline stage, and executing selected transaction requests provided by the arbitrating.

摘要翻译： 一种用于在流水线设备中执行事务的流水线设备和方法，所述方法包括：设置限制器阈值，所述限制器阈值定义将从一个流水线级提供给另一流水线级的待处理事务请求的最大量; 在监视包括流水线限制器的设备的性能的同时执行应用程序; 其中所述执行包括：响应于所述限制器阈值，在某个流水线阶段的事务请求之间进行仲裁，以及执行由所述仲裁提供的所选择的事务请求，选择性地将事务请求从所述流水线的一个级别传送到另一级。

公开(公告)号：US20080256297A1

公开(公告)日：2008-10-16

申请号：US12094123

申请日：2005-11-17

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0851 ,  G06F12/0888

摘要： A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

摘要翻译： 一种包含连接到多个一级缓存单元的多个处理器的设备。 该设备还包括多端口高级缓存单元，其包括第一模块互连，第二模块互连，多个高级缓存路径; 而多个高级缓存路径包括多个可同时访问的交错高级缓存单元。 方便地，该设备还包括至少一个不可缓存的路径。 一种用于从高速缓存检索信息的方法，包括：通过多端口高级缓存单元的第一模块互连并发地接收检索信息的请求。 如果发生至少两个高级缓存命中，则该方法的特征在于从多个高级缓存路径中的至少两个路径提供信息，以及如果发生高级缓存未命中则经由第二模块互连提供信息。

公开(公告)号：US08234452B2

公开(公告)日：2012-07-31

申请号：US12516742

申请日：2006-11-30

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

IPC分类号： G06F12/08 ,  G06F9/30

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F12/0835

摘要： A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

摘要翻译： 一种用于获取指令的设备和方法。 该设备包括适于执行指令的处理器; 适于存储指令的高级存储单元; 由处理器控制的直接存储器访问（DMA）控制器; 包括第一输入端口和第二输入端口的指令高速缓存器; 其中所述指令高速缓冲存储器适于响应于由所述处理器产生并经由所述第一输入端口接收的读取请求向所述处理器提供指令; 其中所述指令高速缓冲存储器还适于响应于由所述DMA控制器生成且经由所述第二输入端口接收的读请求从高级存储器单元获取指令。

公开(公告)号：US08219761B2

公开(公告)日：2012-07-10

申请号：US12094123

申请日：2005-11-17

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yehuda Nowogrodski

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0851 ,  G06F12/0888

摘要： A device that includes multiple processors that are connected to multiple level-one cache units. The device also includes a multi-port high-level cache unit that includes a first modular interconnect, a second modular interconnect, multiple high-level cache paths; whereas the multiple high-level cache paths comprise multiple concurrently accessible interleaved high-level cache units. Conveniently, the device also includes at least one non-cacheable path. A method for retrieving information from a cache that includes: concurrently receiving, by a first modular interconnect of a multiple-port high-level cache unit, requests to retrieve information. The method is characterized by providing information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs.

摘要翻译： 一种包含连接到多个一级缓存单元的多个处理器的设备。 该设备还包括多端口高级缓存单元，其包括第一模块互连，第二模块互连，多个高级缓存路径; 而多个高级缓存路径包括多个可同时访问的交错高级缓存单元。 方便地，该设备还包括至少一个不可缓存的路径。 一种用于从高速缓存检索信息的方法，包括：通过多端口高级缓存单元的第一模块互连并发地接收检索信息的请求。 如果发生至少两个高级缓存命中，则该方法的特征在于从多个高级缓存路径中的至少两个路径提供信息，以及如果发生高级缓存未命中则经由第二模块互连提供信息。

公开(公告)号：US20100070713A1

公开(公告)日：2010-03-18

申请号：US12516742

申请日：2006-11-30

申请人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

发明人： Ron Bercovich ,  Odi Dahan ,  Norman Goldstein ,  Yuval Kfir

IPC分类号： G06F9/30 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/3802 ,  G06F12/0835

摘要： A device and a method for fetching instructions. The device includes a processor adapted to execute instructions; a high level memory unit adapted to store instructions; a direct memory access (DMA) controller that is controlled by the processor; an instruction cache that includes a first input port and a second input port; wherein the instruction cache is adapted to provide instructions to the processor in response to read requests that are generated by the processor and received via the first input port; wherein the instruction cache is further adapted to fetch instructions from a high level memory unit in response to read requests, generated by the DMA controller and received via the second input port.

摘要翻译： 一种用于获取指令的设备和方法。 该设备包括适于执行指令的处理器; 适于存储指令的高级存储单元; 由处理器控制的直接存储器访问（DMA）控制器; 包括第一输入端口和第二输入端口的指令高速缓存器; 其中所述指令高速缓冲存储器适于响应于由所述处理器产生并经由所述第一输入端口接收的读取请求向所述处理器提供指令; 其中所述指令高速缓冲存储器还适于响应于由所述DMA控制器生成且经由所述第二输入端口接收的读请求从高级存储器单元获取指令。

公开(公告)号：US07714386B2

公开(公告)日：2010-05-11

申请号：US11449758

申请日：2006-06-09

申请人： Aaron Anthony Pesetski ,  Hong Zhang ,  John Douglas Adam ,  John Przybysz ,  Jim Murduck ,  Norman Goldstein ,  James Baumgardner

发明人： Aaron Anthony Pesetski ,  Hong Zhang ,  John Douglas Adam ,  John Przybysz ,  Jim Murduck ,  Norman Goldstein ,  James Baumgardner

IPC分类号： H01L27/01

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0554 ,  H01L51/0558

摘要： A carbon nanotube field effect transistor includes a substrate, a source electrode, a drain electrode and a carbon nanotube. The carbon nanotube forms a channel between the source electrode and the drain electrode. The carbon nanotube field effect transistor also includes a gate dielectric and a gate electrode. The gate electrode is separated from the carbon nanotube by the gate dielectric, and an input radio frequency voltage is applied to the gate electrode.

摘要翻译： 碳纳米管场效应晶体管包括基板，源电极，漏电极和碳纳米管。 碳纳米管在源电极和漏电极之间形成通道。 碳纳米管场效应晶体管还包括栅极电介质和栅电极。 栅电极通过栅极电介质与碳纳米管分离，并且将输入射频电压施加到栅电极。

公开(公告)号：USD311881S

公开(公告)日：1990-11-06

申请号：US104674

申请日：1987-10-05

申请人： Shlomo Cohen ,  Norman Goldstein

设计人： Shlomo Cohen ,  Norman Goldstein

公开(公告)号：US20100031020A1

公开(公告)日：2010-02-04

申请号：US12512805

申请日：2009-07-30

申请人： Norman Goldstein

发明人： Norman Goldstein

IPC分类号： H04L9/32 ,  G06F17/30 ,  H04L29/06 ,  G06F15/16

CPC分类号： H04L63/10 ,  G06F21/6245 ,  G06F2221/2141 ,  G06Q10/10

摘要： A system and method is described for managing and securing electronically submitted ideas to a central repository. Users can submit an idea to a central controller which stores that idea in digital form. The user is able to view and update the idea over time, and determine who may or may not have access to the stored files. Access to the stored information is regulated by a central controller. Such control may be dictated by the preferences of the user storing the information. The user may elect to allow only himself to have access to the information, or to allow access to trusted friends or to anyone who enters the central control or website. There is also a method for securing parental/guardian permission to share ideas generated and electronically stored when the idea is generated by a minor.

摘要翻译： 描述了一种用于管理和保护电子提交的想法到中央存储库的系统和方法。 用户可以将想法提交给以数字形式存储该想法的中央控制器。 用户能够随时间查看和更新​​想法，并确定谁可以访问或可能无权访问存储的文件。 访问存储的信息由中央控制器调节。 这种控制可以由存储信息的用户的偏好来决定。 用户可以选择仅允许自己访问该信息，或者允许访问受信任的朋友或进入中央控制或网站的任何人。 还有一种方法来确保父母/监护人的权限，以便在未成年人产生想法时分享生成和电子存储的想法。

公开(公告)号：US20090224230A1

公开(公告)日：2009-09-10

申请号：US11449758

申请日：2006-06-09

申请人： Aaron Anthony Pesetski ,  Hong Zhang ,  John Douglas Adam ,  John Przybysz ,  Jim Murduck ,  Norman Goldstein ,  James Baumgardner

发明人： Aaron Anthony Pesetski ,  Hong Zhang ,  John Douglas Adam ,  John Przybysz ,  Jim Murduck ,  Norman Goldstein ,  James Baumgardner

IPC分类号： H01L29/66 ,  H01L29/786

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0554 ,  H01L51/0558

摘要： A carbon nanotube field effect transistor includes a substrate, a source electrode, a drain electrode and a carbon nanotube. The carbon nanotube forms a channel between the source electrode and the drain electrode. The carbon nanotube field effect transistor also includes a gate dielectric and a gate electrode. The gate electrode is separated from the carbon nanotube by the gate dielectric, and an input radio frequency voltage is applied to the gate electrode.

摘要翻译： 碳纳米管场效应晶体管包括基板，源电极，漏电极和碳纳米管。 碳纳米管在源电极和漏电极之间形成通道。 碳纳米管场效应晶体管还包括栅极电介质和栅电极。 栅电极通过栅极电介质与碳纳米管分离，并且将输入射频电压施加到栅电极。