公开(公告)号：US4291274A

公开(公告)日：1981-09-22

申请号：US096056

申请日：1979-11-20

申请人： Yasoji Suzuki ,  Nobuyuki Kamimaru

发明人： Yasoji Suzuki ,  Nobuyuki Kamimaru

IPC分类号： G01R25/00 ,  H02N2/06 ,  H03D13/00 ,  H03K5/26

CPC分类号： H03D13/004 ,  G01R25/005

摘要： A phase detector circuit having four dominant type flip-flop circuits and at least one logic gate. The phase detector circuit is responsive to changes of two input signals, and produces output signals related to the relative phase of the input signals having duty cycle. The output signals have a predetermined level only for the period the phases of the input signals differ. When the phases of the input signals are the same, the output signals of the phase detector circuit will be at another level.

摘要翻译： 一种具有四个显性触发器电路和至少一个逻辑门的相位检测器电路。 相位检测器电路响应两个输入信号的变化，并且产生与具有占空比的输入信号的相对相关的输出信号。 输出信号仅在输入信号的相位不同的周期内具有预定电平。 当输入信号的相位相同时，相位检测器电路的输出信号将处于另一级。

公开(公告)号：US4545063A

公开(公告)日：1985-10-01

申请号：US497136

申请日：1983-05-23

申请人： Nobuyuki Kamimaru

发明人： Nobuyuki Kamimaru

IPC分类号： H03K23/58 ,  H03K23/64 ,  H03K23/66 ,  H03K21/26

CPC分类号： H03K23/667 ,  H03K23/665

摘要： A programmable counter system of the swallow operation type using binary counters is disclosed. The counter comprises a prescaler for frequency dividing an input signal by a frequency division factor "2.sup.n -1" or "2.sup.n ", upper and lower order bit counters for counting down an output signal from the prescaler, a flip-flop for selecting either the frequency division factor "2.sup.n -1" or "2.sup.n " according to the logical level of the output signal of the counter A or B, and inverters for level inverting programming data and applying them to the lower order bit counter A, thereby setting a division number of the counter A to a complement of the binary code of the programming data.

摘要翻译： 公开了使用二进制计数器的吞咽操作类型的可编程计数器系统。 该计数器包括一个预分频器，用于将输入信号分频为分频因子“2n-1”或“2n”，用于对来自预分频器的输出信号进行计数的上位和下位位计数器，用于选择 根据计数器A或B的输出信号的逻辑电平和电平反转编程数据的反相器分频因子“2n-1”或“2n”，并将其应用于低位位计数器A，从而设定分频 计数器A的编号到编程数据的二进制代码的补码。

公开(公告)号：US4473885A

公开(公告)日：1984-09-25

申请号：US267925

申请日：1981-05-28

申请人： Nobuyuki Kamimaru ,  Hiroaki Suzuki

发明人： Nobuyuki Kamimaru ,  Hiroaki Suzuki

IPC分类号： H03K23/66 ,  H03K21/36

CPC分类号： H03K23/667 ,  H03K23/665

摘要： A frequency dividing ratio setting device capable of successively changing the frequency dividing ratio of a programmable counter and further changing the changed portion of the frequency dividing ratio is provided. The device comprises a circuit for generating a pulse signal corresponding to predetermined data, an adder-subtracter having first and second input terminals and adding or subtracting data supplied to first and second input terminals thereof, said first input terminal being connected to the output terminal of the pulse signal generating circuit, and a shift register to which an output signal is supplied from the adder-subtracter and supplying an input signal to a program terminal of the programmable counter and to the second input terminal of the adder-subtracter.

摘要翻译： 提供了能够连续地改变可编程计数器的分频比并进一步改变分频比的改变部分的分频比设置装置。 该装置包括用于产生对应于预定数据的脉冲信号的电路，具有第一和第二输入端的加法器 - 减法器，以及加到或减去提供给其第一和第二输入端的数据，所述第一输入端连接到 脉冲信号发生电路以及从加法器 - 减法器提供输出信号并将输入信号提供给可编程计数器的程序端和加法器 - 减法器的第二输入端的移位寄存器。