公开(公告)号：US06969904B2

公开(公告)日：2005-11-29

申请号：US10401693

申请日：2003-03-31

申请人： Yasuharu Tsujii ,  Haruaki Morimoto ,  Yutaka Okui

发明人： Yasuharu Tsujii ,  Haruaki Morimoto ,  Yutaka Okui

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/525 ,  H01L29/04

CPC分类号： G11C29/028 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a trimming pattern enabling trimming to be implemented with ease and time required for trimming to be shortened without causing damage to internal elements. The invention provides the trimming pattern for use in trimming of a semiconductor integrated circuit, comprising two pads to which a voltage is applied, a thin line part interconnecting the two pads, and two connecting parts disposed away from each side of the thin line part, and connected to an adjustment circuit and the semiconductor integrated circuit, respectively. With the invention, trimming is executed by a method of turning the adjustment circuit connected to the connecting parts into the ON state by connecting fused metal of the thin line part to the connecting parts. In this case, since the fused metal can be caused to come into contact with the connecting parts nearby with greater ease than fusion cutting of the thin line part, trimming can be implemented with ease and in shorter time.

摘要翻译： 提供了一种修剪图案，其能够轻松实现修剪，并且可以缩短修剪所需的时间，而不会对内部元件造成损害。 本发明提供了用于修整半导体集成电路的修整图案，包括两个施加了电压的焊盘，互连两个焊盘的细线部分和远离细线部分的每一侧的两个连接部分， 并分别连接到调整电路和半导体集成电路。 通过本发明，通过将细线部分的熔融金属连接到连接部分的方法，通过将连接到连接部分的调节电路转到ON状态来进行修整。 在这种情况下，由于熔融金属可以比细线部分的熔合切割更容易地与附近的连接部件接触，所以可以在更短的时间内轻松实现修整。

公开(公告)号：US06326823B1

公开(公告)日：2001-12-04

申请号：US09541428

申请日：2000-04-03

申请人： Yutaka Okui

发明人： Yutaka Okui

IPC分类号： H03L700

CPC分类号： G06F1/025 ,  H03K5/156

摘要： A simplified clock control circuit in which noise and consumed electric power is reduced. When an output signal of a first flip-flop becomes “H” by input of a starting signal, an output signal of a first gate becomes “H”, and a master clock signal given to a second gate is output as a clock signal. The clock signal is counted by a counter, and when the count value becomes a first set value, a trigger signal for starting another clock control portion is output from a first comparator. When the count value becomes a second set value, an operation end signal is output from a second comparator, an output signal of a second flip-flop becomes “L”, and the output signal of the first gate becomes “L”, to stop output of the clock signal.

摘要翻译： 一种简化的时钟控制电路，其中降低了噪声和消耗的电力。 当第一触发器的输出信号通过输入启动信号变为“H”时，第一栅极的输出信号变为“H”，并且输出给第二栅极的主时钟信号作为时钟信号。 时钟信号由计数器计数，当计数值变为第一设定值时，从第一比较器输出用于启动另一个时钟控制部分的触发信号。 当计数值变为第二设定值时，从第二比较器输出运算结束信号，第二触发器的输出信号变为“L”，第一门的输出信号变为“L”，停止 输出时钟信号。