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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07280406B2

    公开(公告)日：2007-10-09

    申请号：US11344199

    申请日：2006-02-01

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor memory device
    3.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41879E1

    公开(公告)日：2010-10-26

    申请号：US12155392

    申请日：2008-06-03

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor storage device
    4.
    发明授权
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US07136313B2

    公开(公告)日：2006-11-14

    申请号：US11121939

    申请日：2005-05-05

    申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

    摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

    摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

    Semiconductor storage device
    5.
    发明申请
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US20050265090A1

    公开(公告)日：2005-12-01

    申请号：US11121939

    申请日：2005-05-05

    申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C29/00 ,  G11C29/12

    CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

    摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

    摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

    Semiconductor memory device
    6.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060171246A1

    公开(公告)日：2006-08-03

    申请号：US11344199

    申请日：2006-02-01

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07485935B2

    公开(公告)日：2009-02-03

    申请号：US11790009

    申请日：2007-04-23

    申请人： Takashi Miki ,  Yasuo Murakuki

    发明人： Takashi Miki ,  Yasuo Murakuki

    IPC分类号： H01L27/088

    CPC分类号： G11C11/22

    摘要： A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.

    摘要翻译： 半导体存储器件具有多个存储单元，多个位线BL，每个位线共同连接到排列在同一行的多个存储单元，多个字线WL和多个板条CP，每个字线和每个 板线通常连接到布置在同一列中的多个存储单元，沿列方向排列的多个板电压供给线CPS，以及用于将多个板电压供给线中的每一个电连接到相应的多个板中的每一个的装置 线条。 板电压供给线由具有低于板线电阻的材料构成，多个存储单元的每个电容器在其周边被氢阻挡膜HB覆盖，多个板电压供给线设置在 在与设置有氢阻挡膜的区域相同的板线的多个位置上的同一板线电连接的情况下，氢阻挡膜HB和多个板电压供给线CPS为同一平面。

    Semiconductor memory device
    9.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20070247889A1

    公开(公告)日：2007-10-25

    申请号：US11790009

    申请日：2007-04-23

    申请人： Takashi Miki ,  Yasuo Murakuki

    发明人： Takashi Miki ,  Yasuo Murakuki

    IPC分类号： G11C17/00

    CPC分类号： G11C11/22

    摘要： A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.

    摘要翻译： 半导体存储器件具有多个存储单元，多个位线BL，每个位线共同连接到排列在同一行的多个存储单元，多个字线WL和多个板条CP，每个字线和每个 板线通常连接到布置在同一列中的多个存储单元，沿列方向排列的多个板电压供给线CPS，以及用于将多个板电压供给线中的每一个电连接到相应的多个板中的每一个的装置 线条。 板电压供给线由具有低于板线电阻的材料构成，多个存储单元的每个电容器在其周边被氢阻挡膜HB覆盖，多个板电压供给线设置在 在与设置有氢阻挡膜的区域相同的板线的多个位置上的同一板线电连接的情况下，氢阻挡膜HB和多个板电压供给线CPS为同一平面。

    Semiconductor memory device
    10.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20070195578A1

    公开(公告)日：2007-08-23

    申请号：US11707157

    申请日：2007-02-16

    申请人： Yasuo Murakuki ,  Takashi Miki

    发明人： Yasuo Murakuki ,  Takashi Miki

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

    摘要翻译： 存储单元阵列由以矩阵排列的多个存储单元组成。 每个存储单元包括：具有连接到公共单元板和存储电极的平板电极的电容器; 以及设置在电容器的存储电极和位线之间的晶体管，栅极连接到字线。 第一放大器将I / O线对放大到高于第一电压的第一电压和第二电压。 第二放大器将位线对放大到第一电压和高于第二电压的第三电压。 开关元件在连接状态，断开状态和限制发送电位的发送限制状态之间切换I / O线对与位线对之间的连接关系。