公开(公告)号：US09097758B2

公开(公告)日：2015-08-04

申请号：US13255523

申请日：2009-03-31

申请人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

发明人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

IPC分类号： G01R31/04 ,  G01R31/28 ,  G01R31/317

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  G01R31/31717

摘要： An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.

摘要翻译： 一种集成电路器件，包括包含在封装中的半导体管芯。 集成电路装置包括一个或多个内部连接验证模块，用于响应于相应的内部电源节点处的电压与参考电压之间的电压差来确定测试装置的不良连接信号，该电压差表示 电源连接到包装上的电源端子之一。 测试装置可以包括用于响应于指示存在或不存在伴随着不良连接信号的不断的缺陷的逻辑信号而拒绝或接受集成电路装置的指示符或分类元件，并且用于处理集成电路 响应于不良连接信号的断言而独立地设备。

公开(公告)号：US20120038367A1

公开(公告)日：2012-02-16

申请号：US13255523

申请日：2009-03-31

申请人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

发明人： Yefim-Haim Fefer ,  Sergey Sofer ,  Boris Zapesochini

IPC分类号： G01R31/04

CPC分类号： G01R31/2853 ,  G01R31/2884 ,  G01R31/31717

摘要： An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal.

摘要翻译： 一种集成电路器件，包括包含在封装中的半导体管芯。 集成电路装置包括一个或多个内部连接验证模块，用于响应于相应的内部电源节点处的电压与参考电压之间的电压差来确定测试装置的不良连接信号，该电压差表示 电源连接到包装上的电源端子之一。 测试装置可以包括用于响应于指示存在或不存在伴随着不良连接信号的不断的缺陷的逻辑信号而拒绝或接受集成电路装置的指示符或分类元件，并且用于处理集成电路 响应于不良连接信号的断言而独立地设备。