公开(公告)号：US06321363B1

公开(公告)日：2001-11-20

申请号：US09228905

申请日：1999-01-11

申请人： Yen-Son Huang ,  Martin Lu ,  Chia-Huei Lee ,  Jensen Tsai

发明人： Yen-Son Huang ,  Martin Lu ,  Chia-Huei Lee ,  Jensen Tsai

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： Prior simulation results and model changes are used to shorten re-simulation time in improved design verification methodology, wherein simulator is re-run on design revision. Accelerated incremental simulation scheme boosts engineer design and verification productivity, and facilitates storage of different design revisions and simulation results.

摘要翻译： 在改进的设计验证方法中，使用先前的仿真结果和模型更改来缩短重新仿真时间，其中模拟器在设计修订上重新运行。 加速增量仿真方案提高了工程师设计和验证的生产力，并促进了不同设计修订和仿真结果的存储。

公开(公告)号：US06446243B1

公开(公告)日：2002-09-03

申请号：US09298320

申请日：1999-04-23

申请人： Yen-Son Huang ,  Chia-Huei Lee ,  Changson Teng

发明人： Yen-Son Huang ,  Chia-Huei Lee ,  Changson Teng

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F2217/66

摘要： Computer-assisted apparatus/method functionally verifies circuit design through automatic generation of verification rules from reusable functional block or IP core using logic simulator and input stimuli. Rule base captures set of design states or scenarios.

摘要翻译： 计算机辅助设备/方法通过使用逻辑模拟器和输入激励从可重用功能块或IP内核自动生成验证规则来功能地验证电路设计。 规则库捕获一组设计状态或场景。

公开(公告)号：US06980211B2

公开(公告)日：2005-12-27

申请号：US10064035

申请日：2002-06-04

申请人： Shyh-Chang Lin ,  Chia-Huei Lee ,  Yu-Sheng Lu ,  Bang-Hwa Ho

发明人： Shyh-Chang Lin ,  Chia-Huei Lee ,  Yu-Sheng Lu ,  Bang-Hwa Ho

IPC分类号： G06F17/50 ,  G06T11/20

CPC分类号： G06T11/206 ,  G06F17/509 ,  G06F2217/74 ,  Y10S715/964

摘要： A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode. Finally, the automatic positioning of components according to predefined topology templates is provided.

摘要翻译： 生成示意图的网表。 网表通过连接线指示组件的连接。 提供了一种正常显示模式，其中至少一部分组件被呈现在显示器上，并且还显示了与组件对应的连接线。 提供了一种拓扑显示模式，其中组件呈现在显示器上而没有连接线。 在编辑原理图时，用户可以在拓扑显示模式和正常显示模式之间进行切换。 根据网表执行连接线的自动引脚分配和布线，并且基于对类似分类的连接线进行分组。 提供了抽象显示模式，其提供了所选组件的抽象行，单个抽象行在两个连接的组件之间运行。 抽象显示模式与拓扑显示模式相结合。 最后，提供了根据预定义的拓扑模板自动定位组件。

公开(公告)号：US06546526B2

公开(公告)日：2003-04-08

申请号：US09764396

申请日：2001-01-19

申请人： Ming-Chih Lai ,  Chia-Huei Lee ,  Bang-Hwa Ho ,  Jien-Shen Tsai

发明人： Ming-Chih Lai ,  Chia-Huei Lee ,  Bang-Hwa Ho ,  Jien-Shen Tsai

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： HDL code is used to describe a circuit in an HDL code debugger on a computer system. Circuit simulation data is obtained for the circuit, the simulation data being generated according to the HDL code. A circuit execution time is selected, and the simulation data should at least span the circuit execution time. A debugging element is selected, which is a circuit element in the circuit having a debugging state at the circuit execution time according to the simulation data. A target line of HDL code is then presented to a user. The target line of HDL code is the line of code responsible for setting the debugging element into the debugging state at the circuit execution time.