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1.发明授权Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control 有权具有线性特性和增强的粗调和微调控制的阻抗匹配输出驱动电路公开(公告)号：US06894529B1
公开(公告)日：2005-05-17
申请号：US10616272
申请日：2003-07-09
IPC分类号： H03K19/00 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein that are responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein that are responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.
摘要翻译： 阻抗匹配的输出驱动器电路包括第一图腾柱驱动器级和第二图腾柱驱动级。 第一图腾柱驱动器级包括分别响应于第一上拉信号和第一下拉信号的至少一个PMOS上拉晶体管和至少一个NMOS下拉晶体管。 第二图腾柱驱动器级具有分别响应于第二上拉信号和第二下拉信号的至少一个NMOS上拉晶体管和至少一个PMOS下拉晶体管。 通过包括在第一和第二图腾柱驱动级之间延伸的第一电阻元件来增强输出驱动器电路的线性度。 第一电阻元件具有第一端子，其电耦合到第一图腾柱驱动器级中的至少一个PMOS上拉晶体管的漏极端子和至少一个NMOS下拉晶体管，以及第二端子，其中 电耦合到第二图腾柱驱动级中的至少一个NMOS上拉晶体管的源极端子和至少一个PMOS下拉晶体管。
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2.发明授权Impedance-matched output driver circuits having coarse and fine tuning control 失效具有粗调和微调控制的阻抗匹配输出驱动电路公开(公告)号：US07123055B1
公开(公告)日：2006-10-17
申请号：US11105237
申请日：2005-04-13
申请人： Yew-Keong Chong , David J. Klein , Brian K. Butka
发明人： Yew-Keong Chong , David J. Klein , Brian K. Butka
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/0005
摘要： Impedance-matched output driver circuits include a first totem pole driver stage and a second totem pole driver stage. The first totem pole driver stage includes at least one PMOS pull-up transistor and at least one NMOS pull-down transistor therein responsive to a first pull-up signal and a first pull-down signal, respectively. The second totem pole driver stage has at least one NMOS pull-up transistor and at least one PMOS pull-down transistor therein responsive to a second pull-up signal and second pull-down signal, respectively. The linearity of the output driver circuit is enhanced by including a first resistive element that extends between the first and second totem pole driver stages. The first resistive element has a first terminal, which is electrically coupled to drain terminals of the at least one PMOS pull-up transistor and the at least one NMOS pull-down transistor in the first totem pole driver stage, and a second terminal, which is electrically coupled to source terminals of the at least one NMOS pull-up transistor and the at least one PMOS pull-down transistor in the second totem pole driver stage.
摘要翻译： 阻抗匹配的输出驱动器电路包括第一图腾柱驱动器级和第二图腾柱驱动级。 第一图腾柱驱动级包括分别响应于第一上拉信号和第一下拉信号的至少一个PMOS上拉晶体管和至少一个NMOS下拉晶体管。 第二图腾柱驱动级具有分别响应于第二上拉信号和第二下拉信号的至少一个NMOS上拉晶体管和至少一个PMOS下拉晶体管。 通过包括在第一和第二图腾柱驱动级之间延伸的第一电阻元件来增强输出驱动器电路的线性度。 第一电阻元件具有第一端子，其电耦合到第一图腾柱驱动器级中的至少一个PMOS上拉晶体管的漏极端子和至少一个NMOS下拉晶体管，以及第二端子，其中 电耦合到第二图腾柱驱动级中的至少一个NMOS上拉晶体管的源极端子和至少一个PMOS下拉晶体管。
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公开(公告)号：US20090103391A1
公开(公告)日：2009-04-23
申请号：US11907818
申请日：2007-10-17
申请人： Gus Yeung , Yew-Keong Chong
发明人： Gus Yeung , Yew-Keong Chong
IPC分类号： G11C8/18
摘要： An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry 18 generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path 26 to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory 4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.
摘要翻译： 具有存储器4的集成电路2设置有时钟发生器电路18.时钟发生器电路18在第一模式下操作，其中根据源时钟的上升沿和下降沿两者来产生存储器时钟信号mclk 信号sclk。 在第二操作模式中，时钟发生器电路18在源时钟信号sclk的上升沿之后产生存储器时钟信号mclk，然后使用自定时延迟路径26触发存储器时钟信号mclk的下降沿。 第一种操作模式可以在写入操作期间和在读取操作期间在存储器4的多个不同的动态可选择的电压电平中的最低的一个中使用。在读取期间可以使用第二种自定时存储器时钟信号模式 在最低工作电压以外的工作电压。
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公开(公告)号：US07660186B2
公开(公告)日：2010-02-09
申请号：US11907818
申请日：2007-10-17
申请人： Gus Yeung , Yew-Keong Chong
发明人： Gus Yeung , Yew-Keong Chong
IPC分类号： G11C8/00
摘要： An integrated circuit 2 with a memory 4 is provided with clock generator circuitry 18. The clock generator circuitry 18 operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry 18 generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path 26 to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory 4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.
摘要翻译： 具有存储器4的集成电路2设置有时钟发生器电路18.时钟发生器电路18在第一模式下操作，其中根据源时钟的上升沿和下降沿两者来产生存储器时钟信号mclk 信号sclk。 在第二操作模式中，时钟发生器电路18在源时钟信号sclk的上升沿之后产生存储器时钟信号mclk，然后使用自定时延迟路径26触发存储器时钟信号mclk的下降沿。 第一种操作模式可以在写入操作期间和在读取操作期间在存储器4的多个不同的动态可选择的电压电平中的最低的一个中使用。在读取期间可以使用第二种自定时存储器时钟信号模式 在最低工作电压以外的工作电压。
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