利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.029 秒)

    Parallel data path architecture for high energy efficiency
    1.
    发明申请
    Parallel data path architecture for high energy efficiency 有权
    并行数据路径架构，实现高能效

    公开(公告)号：US20060112258A1

    公开(公告)日：2006-05-25

    申请号：US11144703

    申请日：2005-06-06

    申请人： Yil Yang ,  Tae Roh ,  Dae Lee ,  Sang Lee ,  Jong Kim

    发明人： Yil Yang ,  Tae Roh ,  Dae Lee ,  Sang Lee ,  Jong Kim

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/30141 ,  G06F9/30156 ,  G06F9/3822 ,  G06F9/3824 ,  Y02D10/171

    摘要： Provided is a parallel data path architecture for high energy efficiency. In this architecture, a plurality of parallel process units and a plurality of function units of the process units are controlled by instructions and processed in parallel to improve performance. Also, since only necessary process units and function units are enabled, power dissipation is reduced to enhance energy efficiency. Further, by use of a simple instruction format, hardware can be programmed as the parallel data path architecture for high energy efficiency, which satisfies both excellent performance and low power dissipation, thus elevating hardware flexibility.

    摘要翻译： 提供了一种用于高能效的并行数据路径架构。 在该架构中，处理单元的多个并行处理单元和多个功能单元由指令控制并且并行处理以提高性能。 此外，由于只需要必要的处理单元和功能单元，所以功耗降低以提高能量效率。 此外，通过使用简单的指令格式，可以将硬件编程为用于高能量效率的并行数据路径体系结构，其既能满足优异性能又具有低功耗，从而提高硬件灵活性。

    Sources driver circuit for active matrix electroluminescent display and driving method thereof
    3.
    发明申请
    Sources driver circuit for active matrix electroluminescent display and driving method thereof 有权
    用于有源矩阵电致发光显示器的源极驱动电路及其驱动方法

    公开(公告)号：US20050140595A1

    公开(公告)日：2005-06-30

    申请号：US10817838

    申请日：2004-04-06

    申请人： Yil Yang ,  Jong Kim ,  Dae Lee ,  Tae Roh ,  Il Park ,  Sung Kwon ,  Byoung Yu

    发明人： Yil Yang ,  Jong Kim ,  Dae Lee ,  Tae Roh ,  Il Park ,  Sung Kwon ,  Byoung Yu

    IPC分类号： G09G3/30

    CPC分类号： G09G3/30 ,  G09G2310/027 ,  G09G2320/0276

    摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.

    摘要翻译： 提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度 的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

    Latch circuit and flip-flop
    4.
    发明申请
    Latch circuit and flip-flop 有权
    锁存电路和触发器

    公开(公告)号：US20070132495A1

    公开(公告)日：2007-06-14

    申请号：US11520165

    申请日：2006-09-13

    申请人： Yil Yang ,  Jong Kim ,  Tae Roh ,  Dae Lee

    发明人： Yil Yang ,  Jong Kim ,  Tae Roh ,  Dae Lee

    IPC分类号： H03K3/00

    CPC分类号： H03K19/0013 ,  H03K3/356156 ,  H03K3/356182

    摘要： A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit having low sub-threshold leakage current is provided. More particularly, a latch circuit and flip-flop that can be applied in the deep sub-micron era and that are entirely configured of only CMOS using a combination of a high threshold device and a low threshold device and a low-threshold-voltage stack structure, without using a power gating technique such as multi-threshold CMOS (MTCMOS) and a back bias voltage control technique such as variable threshold CMOS (VTCMOS), are provided. The multi-threshold latch circuit includes: a forward clock inverter including a low threshold transistor only and inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a backward clock inverter including a high threshold transistor, forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.

    摘要翻译： 提供了具有低亚阈值泄漏电流的高可靠性，多阈值互补金属氧化物半导体（CMOS）锁存电路。 更具体地，可以应用于深亚微米时代的锁存电路和触发器，并且仅使用高阈值器件和低阈值器件和低阈值电压堆叠的组合的CMOS构成 结构，而不使用诸如多阈值CMOS（MTCMOS）的功率门控技术和诸如可变阈值CMOS（VTCMOS）的背偏压控制技术。 多阈值锁存电路包括：正时时钟反相器，其仅在低阈值晶体管和反相输入端逻辑状态下进行反相，并且当时钟处于第一逻辑状态时将反相逻辑状态应用于输出端逻辑状态; 以及包括高阈值晶体管的反向时钟反相器，与正向时钟反相器一起形成圆形锁存结构，并且当时钟处于第二逻辑时反相输入端逻辑状态并将反相逻辑状态应用于输出逻辑状态 州。