公开(公告)号：US07571086B2

公开(公告)日：2009-08-04

申请号：US11267726

申请日：2005-11-04

申请人： Ying-Tsai Chang ,  Tayung Liu ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Tayung Liu ,  Yu-Chin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval. Before the initial full-circuit simulation, each signal is classified as an essential signal when its behavior during the full-circuit simulation must be represented by the first simulation data in order to provide sufficient information to program the simulator to re-simulate the behavior any selected subcircuit during any selected subinterval. All other circuit signals are classified as non-essential signals whose behavior need not be represented by the saved first simulation data.

摘要翻译： 处理电路的网表描述，将电路的一些信号分类为基本信号，并将电路的所有其他信号分类为非必要信号。 此后，当模拟响应于在一段时间间隔内提供的输入信号的整个电路的行为时，模拟器在时间间隔期间保存表示电路的基本信号的行为的第一仿真数据。 此后，根据由第一仿真数据描述的基本信号的行为，将模拟器编程为仅在全时间间隔的选定子间隔期间再次仅模拟电路的选定子电路的行为。 在重新仿真期间，模拟器保存表示子电路的基本信号和非必要信号的二次仿真数据，以提供所选择的子间隔期间所选择的子电路的行为的更完整的图像。 在初始全电路仿真之前，每个信号被分类为必要信号，当其全电路仿真期间的行为必须由第一仿真数据表示，以便提供足够的信息来编程仿真器以重新模拟任何 在任何选择的子间隔期间选择子电路。 所有其他电路信号被分类为非必要信号，其行为不需要由保存的第一模拟数据表示。

公开(公告)号：US20070106488A1

公开(公告)日：2007-05-10

申请号：US11267726

申请日：2005-11-04

申请人： Ying-Tsai Chang ,  Tayung Liu ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Tayung Liu ,  Yu-Chin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A netlist description of a circuit is processed to classify some signals of the circuit as essential signals and to classify all other signals of the circuit as non-essential signals. Thereafter when simulating behavior of the entire circuit in response to input signals supplied over some time interval, a simulator saves first simulation data representing behavior of the circuit's essential signals during the time interval. Thereafter the simulator is programmed to re-simulate behavior of only a selected subcircuit of the circuit during only a selected subinterval of the full time interval based on behavior of essential signals described by the first simulation data. During the re-simulation, the simulator saves second simulation data representing behavior of both essential and non-essential signals of the subcircuit to provide a more complete picture of the behavior of the selected subcircuit during the selected subinterval. Before the initial full-circuit simulation, each signal is classified as an essential signal when its behavior during the full-circuit simulation must be represented by the first simulation data in order to provide sufficient information to program the simulator to re-simulate the behavior any selected subcircuit during any selected subinterval. All other circuit signals are classified as non-essential signals whose behavior need not be represented by the saved first simulation data

摘要翻译： 处理电路的网表描述，将电路的一些信号分类为基本信号，并将电路的所有其他信号分类为非必要信号。 此后，当模拟响应于在一段时间间隔内提供的输入信号的整个电路的行为时，模拟器在时间间隔期间保存表示电路的基本信号的行为的第一仿真数据。 此后，根据由第一仿真数据描述的基本信号的行为，将模拟器编程为仅在全时间间隔的选定子间隔期间再次仅模拟电路的选定子电路的行为。 在重新仿真期间，模拟器保存表示子电路的基本信号和非必要信号的二次仿真数据，以提供所选择的子间隔期间所选择的子电路的行为的更完整的图像。 在初始全电路仿真之前，每个信号被分类为必要信号，当其全电路仿真期间的行为必须由第一仿真数据表示，以便提供足够的信息来编程仿真器以重新模拟任何 在任何选择的子间隔期间选择子电路。 所有其他电路信号被分类为非必要信号，其行为不需要由保存的第一模拟数据表示

公开(公告)号：US07079997B1

公开(公告)日：2006-07-18

申请号：US10143347

申请日：2002-05-10

申请人： Yu-Chin Hsu ,  Furshing Tsai ,  Yirng-An Chen ,  Kunming Ho ,  Tayung Liu ,  Chieh Changfan ,  Wells Woei-Tzy Jong

发明人： Yu-Chin Hsu ,  Furshing Tsai ,  Yirng-An Chen ,  Kunming Ho ,  Tayung Liu ,  Chieh Changfan ,  Wells Woei-Tzy Jong

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement. Each statement event symbol references the signal whose value is computed by the corresponding statement evaluation and indicates a value of that signal computed when the statement was evaluated. Each statement event symbol also references the other signals having values of which the statement indicates the computed signal value is a function and indicates those other signals values as of the simulation time at which the statement was evaluated.

摘要翻译： 调试器根据由电路仿真器或验证工具执行的指令以及在执行指令时由仿真器或验证工具产生的波形数据产生显示。 指令包括一组语句，每个语句对应于由电路产生的单独的电路信号，并且每个语句包括定义电路信号的值作为其他电路信号的值的函数的函数。 模拟器在各种模拟时间对语句进行评估，以在这些模拟时间计算信号值。 波形数据表示模拟器在评估语句时计算的信号值。 调试器显示包括一组语句事件符号，每个对应于语句的单独评估，并且每个语句事件符号分别位于显示器中，以指示模拟器评估该语句的模拟时间。 每个语句事件符号引用其值由相应的语句评估计算的信号，并指示在评估语句时计算的该信号的值。 每个语句事件符号还引用具有值的其他信号，其中语句指示计算的信号值是函数，并且指示在评估语句时的模拟时间的那些其他信号值。

公开(公告)号：US07031899B2

公开(公告)日：2006-04-18

申请号：US09829535

申请日：2001-04-09

申请人： Yu-Chin Hsu ,  Furshing Tsai ,  Tayung Liu ,  Bassam Tabbara ,  Kunming Ho ,  George Bakewell ,  Yirng-An Chen ,  Scott Sandler

发明人： Yu-Chin Hsu ,  Furshing Tsai ,  Tayung Liu ,  Bassam Tabbara ,  Kunming Ho ,  George Bakewell ,  Yirng-An Chen ,  Scott Sandler

IPC分类号： G06F3/147 ,  G06F3/153

CPC分类号： G06F17/5022

摘要： A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

公开(公告)号：US08281280B2

公开(公告)日：2012-10-02

申请号：US13025809

申请日：2011-02-11

申请人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.

摘要翻译： 用于测试验证设计（DUV）的方法和系统，所述方法包括在接口处接收配置的现场可编程门阵列（FPGA）图像和运行时间控制信息，其中每个FPGA图像包含DUV的相应部分， 以及与相应的FPGA器件相关联的相应的验证模块。 该方法还包括：通过接口将每个FPGA图像发送到与每个相应FPGA图像相关联的每个相应的FPGA器件。 该方法还包括：基于从主机工作站接收的运行时控制信息，通过接口将定时和控制信息发送到各个验证模块。 响应于接收到的定时和控制信息，各个验证模块中的每一个控制各个FPGA器件中的每一个的DUV的各个部分。

公开(公告)号：US06985840B1

公开(公告)日：2006-01-10

申请号：US09630348

申请日：2000-07-31

申请人： Yu-Chin Hsu ,  Furshing Tsai ,  Tayung Liu

发明人： Yu-Chin Hsu ,  Furshing Tsai ,  Tayung Liu

IPC分类号： G06F7/48

CPC分类号： G01R31/3181 ,  G01R31/3183 ,  G01R31/318314

摘要： Described herein is a system for verifying that a circuit described by a hardware description language file has a property of responding to an antecedent event represented by a particular pattern in its input signals by exhibiting a consequent behavior of producing a particular pattern in its output signals during a finite time following the antecedent event. The system includes a conventional circuit simulator for simulating the behavior of the circuit under conditions defined by a user-provided test bench. The simulator produces output waveform data representing the behavior of the circuit input, output and internal signals, including signals representing the circuit's state. When the output waveform data indicates the antecedent event has occurred, the system determines the current state of the circuit from the waveform data. The system then creates and analyzes a temporally expanded model of the circuit to verify whether, starting from that current state, the circuit will exhibit the consequent behavior within that finite time under all input signal conditions.

摘要翻译： 这里描述了一种用于验证由硬件描述语言文件描述的电路具有响应于其输入信号中由特定模式表示的先行事件的性质的系统，其表现出在其输出信号中产生特定模式的结果行为 在先前事件之后的有限时间。 该系统包括用于在由用户提供的测试台定义的条件下模拟电路的行为的常规电路仿真器。 模拟器产生表示电路输入，输出和内部信号的行为的输出波形数据，包括表示电路状态的信号。 当输出波形数据表示先前事件发生时，系统根据波形数据确定电路的当前状态。 然后，系统创建并分析电路的时间扩展模型，以验证从该当前状态开始，电路是否将在所有输入信号条件下的有限时间内展现出相应的行为。

公开(公告)号：US20110202894A1

公开(公告)日：2011-08-18

申请号：US13025809

申请日：2011-02-11

申请人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

发明人： Ying-Tsai Chang ,  Hwa Mao ,  Swey-Yan Shei ,  Ming-Yang Wang ,  Yu-Chin Hsu

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5027

摘要： Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design.

摘要翻译： 用于测试原型的方法和系统，所述方法包括在第一接口部件处接收与代表用户设计的至少一部分的配置图像相关联的配置参数和相关联的验证模块。 该方法还包括：使用第一接口组件将配置的图像发送到设备。 第二接口部件可以被配置为基于从第一接口部件接收到的配置图像和运行时间控制信息中的至少一个来向定时模块发送定时和控制信息。 响应于从第二接口部件接收定时和控制信息，验证模块可以控制设备和/或监视用户设计的至少一部分的设备状态。

公开(公告)号：USD586565S1

公开(公告)日：2009-02-17

申请号：US29309274

申请日：2008-07-17

申请人： Ti-Chieh Ko ,  Cheng-Han Hsieh ,  Yu-Chin Hsu

设计人： Ti-Chieh Ko ,  Cheng-Han Hsieh ,  Yu-Chin Hsu

公开(公告)号：USD591262S1

公开(公告)日：2009-04-28

申请号：US29290359

申请日：2007-11-27

申请人： Ti-Chieh Ko ,  Cheng-Han Hsieh ,  Mei-Chun Liu ,  Yu-Chin Hsu

设计人： Ti-Chieh Ko ,  Cheng-Han Hsieh ,  Mei-Chun Liu ,  Yu-Chin Hsu

公开(公告)号：US20070125868A1

公开(公告)日：2007-06-07

申请号：US11437663

申请日：2006-05-22

申请人： Min-Kao Hong ,  Chie-Chung Kuo ,  Yu-Chin Hsu ,  Vivian Wang

发明人： Min-Kao Hong ,  Chie-Chung Kuo ,  Yu-Chin Hsu ,  Vivian Wang

IPC分类号： G06K19/06

CPC分类号： A61J1/03 ,  A61J7/0418 ,  A61J2200/30 ,  A61J2205/60 ,  A61J2205/70

摘要： A disposable serial package and its monitoring system are proposed. Conductive structures are provided on each of several package units detachably attached in series forming the disposable serial package. Each conductive structure has several leads and each of the leads has a front end and a tail end. The tail end of a second lead being connected to a first lead on the same conductive structure and a third lead of any one of the package units is connected to the front end of the second lead of a succeeding package unit. A monitoring device is cooperatively used to allow setting of the quantity of package units to be monitored and the instantaneous quantity of package units based on the conducting state of the leads.

摘要翻译： 提出了一次性串行包及其监控系统。 导电结构设置在几个可拆卸地串联连接形成一次性串行封装的封装单元中。 每个导电结构具有多个引线，并且每个引线具有前端和尾端。 第二引线的尾端连接到同一导电结构上的第一引线，并且任一个封装单元的第三引线连接到后续封装单元的第二引线的前端。 协调使用监控装置，以便基于引线的导通状态来设定要监视的封装单元的数量和封装单元的瞬时量。