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公开(公告)号：US07043657B1
公开(公告)日：2006-05-09
申请号：US10682741
申请日：2003-10-08
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.
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公开(公告)号：US06937664B1
公开(公告)日：2005-08-30
申请号：US09617592
申请日：2000-07-18
申请人： Yong E. Park , Jeongsik Yang , Shuen-Chin Chang , Young Gon Kim , Chiayao S. Tung , Cindy Y. Ng
发明人： Yong E. Park , Jeongsik Yang , Shuen-Chin Chang , Young Gon Kim , Chiayao S. Tung , Cindy Y. Ng
CPC分类号： H04L25/49
摘要： An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.
摘要翻译： 一种用于提供多符号信令的装置包括多符号编码器电路。 多符号编码器电路可操作以将数据编码为多个符号，每个符号由载波信号中的信号转换和信号区域唯一地定义。 耦合到多符号编码器电路的驱动器电路可操作以驱动载波信号。
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公开(公告)号：US07167527B1
公开(公告)日：2007-01-23
申请号：US10139047
申请日：2002-05-02
申请人： Yong E. Park , Shuen-Chin Chang , Chiayao S. Tung
发明人： Yong E. Park , Shuen-Chin Chang , Chiayao S. Tung
CPC分类号： H04L25/4917 , H04L25/4923
摘要： In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.
摘要翻译： 在一个方面，提供了用于以载波信号中传送的传输符号的形式传送数据的装置和方法，其中每个传输符号来自包括多个符号的符号集合，这些符号集合能够表示任何值的组合 至少三位的数据，其中符号集合的每个符号在载波信号中至多一个信号电平的转变被定义。 在另一方面，提供了装置和方法，用于传送在载波信号中传送的相应传输符号形式的至少三个数据位的值的任何组合，其中传输符号由信号电平 转换，信号电平转换不足，信号区域以及载波信号中的信号区域之间的交叉。
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4.发明授权Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle 失效即使两个信号之间的相位延迟大于一个周期，也可以使用单个正向和反向时钟信号导出通用同步时钟信号公开(公告)号：US06647506B1
公开(公告)日：2003-11-11
申请号：US09452274
申请日：1999-11-30
IPC分类号： G06F104
CPC分类号： G06F1/10
摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.
摘要翻译： 同步总线系统包括具有连接到多个设备中的每一个的正向时钟段和反向时钟段的时钟线。 正向时钟段承载正向时钟信号，反向时钟段承载反向时钟信号。 在每个设备中提供的同步时钟电路接收正向时钟信号和反向时钟信号。 使用接收到的时钟信号，同步时钟电路产生通用同步时钟信号，其在所有设备中是同步的。 提供在装置的至少一部分中的偏斜校正电路校正通用同步时钟信号与用于在设备之间传送数据的一个或多个数据信号之间的偏斜。
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5.发明授权System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream 失效用于半导体芯片的I / O接口的系统利用在第一数据流中向每个数据元素添加参考元素并解释以恢复第二数据流的数据元素公开(公告)号：US06477592B1
公开(公告)日：2002-11-05
申请号：US09369636
申请日：1999-08-06
申请人： Jawji Chen , Shuen-Chin Chang , Yong E. Park , Cindy Yuklin Ng , Chiayao S. Tung , Jeongsik Yang
发明人： Jawji Chen , Shuen-Chin Chang , Yong E. Park , Cindy Yuklin Ng , Chiayao S. Tung , Jeongsik Yang
IPC分类号： G06F1320
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1066
摘要： An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.
摘要翻译： I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。
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公开(公告)号：US20110115564A1
公开(公告)日：2011-05-19
申请号：US12938292
申请日：2010-11-02
申请人： Chiayao S. Tung
发明人： Chiayao S. Tung
IPC分类号： H02H7/20
CPC分类号： H03F1/523 , H03F2200/456
摘要： In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.
摘要翻译： 在一个实施例中，一种方法包括：在输出节点处检测短对地条件和短路供应条件之一; 根据检测选择性地激活反馈控制晶体管; 使用尺寸设定为小于所述第一晶体管的第二晶体管来检测通过第一晶体管的第一电流; 使用多个晶体管镜像检测到的电流以形成反馈电流; 以及根据所述反馈控制晶体管的选择性地激活来向第一晶体管的栅电极提供反馈电流。
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公开(公告)号：US08154346B2
公开(公告)日：2012-04-10
申请号：US12938292
申请日：2010-11-02
申请人： Chiayao S. Tung
发明人： Chiayao S. Tung
IPC分类号： H02H7/20
CPC分类号： H03F1/523 , H03F2200/456
摘要： In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.
摘要翻译： 在一个实施例中，一种方法包括：在输出节点处检测短对地条件和短路供应条件之一; 根据检测选择性地激活反馈控制晶体管; 使用尺寸设定为小于所述第一晶体管的第二晶体管来检测通过第一晶体管的第一电流; 使用多个晶体管镜像检测到的电流以形成反馈电流; 以及根据所述反馈控制晶体管的选择性地激活来向第一晶体管的栅电极提供反馈电流。
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