公开(公告)号：US06477592B1

公开(公告)日：2002-11-05

申请号：US09369636

申请日：1999-08-06

申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

IPC分类号： G06F1320

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

摘要： An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

摘要翻译： I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。

公开(公告)号：US06647506B1

公开(公告)日：2003-11-11

申请号：US09452274

申请日：1999-11-30

申请人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

发明人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

摘要翻译： 同步总线系统包括具有连接到多个设备中的每一个的正向时钟段和反向时钟段的时钟线。 正向时钟段承载正向时钟信号，反向时钟段承载反向时钟信号。 在每个设备中提供的同步时钟电路接收正向时钟信号和反向时钟信号。 使用接收到的时钟信号，同步时钟电路产生通用同步时钟信号，其在所有设备中是同步的。 提供在装置的至少一部分中的偏斜校正电路校正通用同步时钟信号与用于在设备之间传送数据的一个或多个数据信号之间的偏斜。

公开(公告)号：US07043657B1

公开(公告)日：2006-05-09

申请号：US10682741

申请日：2003-10-08

申请人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

发明人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

公开(公告)号：US06937664B1

公开(公告)日：2005-08-30

申请号：US09617592

申请日：2000-07-18

申请人： Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

发明人： Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

IPC分类号： H04L25/49 ,  H04L27/00

CPC分类号： H04L25/49

摘要： An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

摘要翻译： 一种用于提供多符号信令的装置包括多符号编码器电路。 多符号编码器电路可操作以将数据编码为多个符号，每个符号由载波信号中的信号转换和信号区域唯一地定义。 耦合到多符号编码器电路的驱动器电路可操作以驱动载波信号。

公开(公告)号：US07167527B1

公开(公告)日：2007-01-23

申请号：US10139047

申请日：2002-05-02

申请人： Yong E. Park ,  Shuen-Chin Chang ,  Chiayao S. Tung

发明人： Yong E. Park ,  Shuen-Chin Chang ,  Chiayao S. Tung

IPC分类号： H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC分类号： H04L25/4917 ,  H04L25/4923

摘要： In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

摘要翻译： 在一个方面，提供了用于以载波信号中传送的传输符号的形式传送数据的装置和方法，其中每个传输符号来自包括多个符号的符号集合，这些符号集合能够表示任何值的组合 至少三位的数据，其中符号集合的每个符号在载波信号中至多一个信号电平的转变被定义。 在另一方面，提供了装置和方法，用于传送在载波信号中传送的相应传输符号形式的至少三个数据位的值的任何组合，其中传输符号由信号电平 转换，信号电平转换不足，信号区域以及载波信号中的信号区域之间的交叉。

公开(公告)号：US06324602B1

公开(公告)日：2001-11-27

申请号：US09135986

申请日：1998-08-17

申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

IPC分类号： G06F1338

CPC分类号： H03M7/30 ,  G11C7/1006 ,  G11C11/56 ,  H03M5/02

摘要： An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

摘要翻译： 为具有可通过两级协议格式化的信号访问的存储器存储阵列的集成电路存储器提供高级输入/输出接口。 高级输入/输出接口包括一个位压缩电路，用于接收以两电平协议格式化并在集成电路存储器内产生的第一组多个信号。 比特压缩电路将第一多个两级协议信号转换成以多级协议格式化的第一信号。 一个解压缩电路接收以多级协议格式化的第二信号。 比特解压缩电路将第二多级协议信号转换为以两级协议格式化的第二多个信号。 在一个实施例中，高级输入/输出接口允许高速/带宽存储器访问，同时减少了操作所需的引脚数和操作频率。

公开(公告)号：US5153459A

公开(公告)日：1992-10-06

申请号：US206824

申请日：1988-06-15

申请人： Yong E. Park ,  Soo I. Cho ,  Dong S. Jun ,  Seung M. Seo

发明人： Yong E. Park ,  Soo I. Cho ,  Dong S. Jun ,  Seung M. Seo

IPC分类号： G11C11/4093 ,  G11C11/409 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/409

摘要： An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle. The data transmission circuit is characterized in that each of the inverting stages can operate under the control of a block selecting clock signal regardless of the precharging voltages of the true and complement I/O bus lines.

摘要翻译： 描述了一种用于互补金属氧化物半导体（CMOS）动态随机存取存储器件的改进的数据传输电路，其具有用于将晶体管晶体管逻辑（TTL）输入数据信号转换为CMOS逻辑电平真实和补码数据信号的数据输入缓冲器。 数据传输电路包括一对传输门，用于在写入周期内传送真实和补码数据信号，连接在相应传输门之间的一对反相级和真和补输入/输出（I / O）总线 用于反转来自传输门的数据信号，以便在写入周期中将反相数据信号提供给真实和补码I / O总线，以及用于在预充电周期中对真和互补I / O总线进行预充电和均衡的均衡级。 数据传输电路的特征在于，不管真和互补I / O总线的预充电电压如何，每个反相级可在块选择时钟信号的控制下工作。