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    Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle
    3.
    发明授权
    Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle 失效
    即使两个信号之间的相位延迟大于一个周期，也可以使用单个正向和反向时钟信号导出通用同步时钟信号

    公开(公告)号：US06647506B1

    公开(公告)日：2003-11-11

    申请号：US09452274

    申请日：1999-11-30

    申请人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

    发明人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

    IPC分类号： G06F104

    CPC分类号： G06F1/10

    摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

    摘要翻译： 同步总线系统包括具有连接到多个设备中的每一个的正向时钟段和反向时钟段的时钟线。 正向时钟段承载正向时钟信号，反向时钟段承载反向时钟信号。 在每个设备中提供的同步时钟电路接收正向时钟信号和反向时钟信号。 使用接收到的时钟信号，同步时钟电路产生通用同步时钟信号，其在所有设备中是同步的。 提供在装置的至少一部分中的偏斜校正电路校正通用同步时钟信号与用于在设备之间传送数据的一个或多个数据信号之间的偏斜。

    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
    4.
    发明授权
    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream 失效
    用于半导体芯片的I / O接口的系统利用在第一数据流中向每个数据元素添加参考元素并解释以恢复第二数据流的数据元素

    公开(公告)号：US06477592B1

    公开(公告)日：2002-11-05

    申请号：US09369636

    申请日：1999-08-06

    申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    IPC分类号： G06F1320

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

    摘要： An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

    摘要翻译： I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。

    FAST-SWITCHING LOW-NOISE CHARGE PUMP
    5.
    发明申请
    FAST-SWITCHING LOW-NOISE CHARGE PUMP 有权
    快速切换低噪声充电泵

    公开(公告)号：US20110291716A1

    公开(公告)日：2011-12-01

    申请号：US13208456

    申请日：2011-08-12

    申请人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    发明人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0896 ,  H03L7/18

    摘要： In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

    摘要翻译： 在本发明的一个实施例中，公开了一种用于电荷泵的方法。 该方法包括偏置多个晶体管; 切换一对主晶体管开关以通过偏置晶体管施加或去除输出端子上的净电荷; 并且当主晶体管开关断开时，接通辅助晶体管开关。 辅助晶体管开关导通时，为主晶体管开关和偏置晶体管之间的节点提供辅助均衡通路。 辅助均衡路径均衡中间节点之间的电压，以快速关闭偏置晶体管，并降低电荷泵输出端子上的噪声。

    Low power wideband LO using tuned injection locked oscillator
    6.
    发明授权
    Low power wideband LO using tuned injection locked oscillator 有权
    低功耗宽带LO使用调谐注入锁定振荡器

    公开(公告)号：US08704603B2

    公开(公告)日：2014-04-22

    申请号：US13086325

    申请日：2011-04-13

    申请人： Mazhareddin Taghivand ,  Jeongsik Yang

    发明人： Mazhareddin Taghivand ,  Jeongsik Yang

    IPC分类号： H03B5/12 ,  H03B27/00 ,  H03L7/24 ,  H03L7/06

    CPC分类号： H03L7/18 ,  H03B19/14 ,  H03B2200/0078 ,  H03J2200/10

    摘要： A tunable Injection-Locked Oscillator (ILO) having a wide locking range is used in a Local Oscillator (LO) of a wideband wireless transceiver to generate differential signals. The ILO includes a resonator with an adjustable natural oscillating frequency. In one example, the ILO is part of a quadrature divider that can lock onto a Phase-Locked Loop (PLL) output signal in a wide frequency band while achieving lower power consumption and lower phase noise than a differential latch type divider. The ILO is tuned by disabling a Voltage-Controlled Oscillator (VCO) from driving the ILO, adjusting the natural oscillating frequency, making a measurement indicative of the natural oscillating frequency, and determining whether the measurement is within a predetermined range. If the measurement is below the predetermined range, capacitances of resonators within the ILO are decreased, whereas if the measurement is above the predetermined range, capacitances of the resonators are increased.

    摘要翻译： 在宽带无线收发器的本地振荡器（LO）中使用具有宽锁定范围的可调注入锁定振荡器（ILO）以产生差分信号。 国际劳工组织包括具有可调节的自然振荡频率的谐振器。 在一个示例中，国际劳工组织是正交分频器的一部分，其可以在宽频带内锁定锁相环（PLL）输出信号，同时实现比差分锁存器类型分频器更低的功耗和更低的相位噪声。 国际劳工组织通过禁用驱动国际劳工组织的电压控制振荡器（VCO）进行调整，调整自然振荡频率，进行表示自然振荡频率的测量，以及确定测量是否在预定范围内。 如果测量低于预定范围，则国际劳工组织内的谐振器的电容减小，而如果测量高于预定范围，则谐振器的电容增加。

    SYSTEM FOR I-Q PHASE MISMATCH DETECTION AND CORRECTION
    7.
    发明申请
    SYSTEM FOR I-Q PHASE MISMATCH DETECTION AND CORRECTION 有权
    用于I-Q相位误差检测和校正的系统

    公开(公告)号：US20120187994A1

    公开(公告)日：2012-07-26

    申请号：US13011716

    申请日：2011-01-21

    申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

    发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

    IPC分类号： H03K5/00

    CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

    摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

    摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

    AUXILIARY VARACTOR FOR TEMPERATURE COMPENSATION
    9.
    发明申请
    AUXILIARY VARACTOR FOR TEMPERATURE COMPENSATION 有权
    用于温度补偿的辅助变量

    公开(公告)号：US20090261917A1

    公开(公告)日：2009-10-22

    申请号：US12107592

    申请日：2008-04-22

    申请人： Mazhareddin Taghivand ,  Conor Donovan ,  Jeongsik Yang ,  Sang-Oh Lee

    发明人： Mazhareddin Taghivand ,  Conor Donovan ,  Jeongsik Yang ,  Sang-Oh Lee

    IPC分类号： H03L1/02

    CPC分类号： H03L1/023 ,  H03L1/025

    摘要： Techniques for compensating for the effects of temperature change on voltage controlled oscillator (VCO) frequency are disclosed. In an embodiment, an auxiliary varactor is coupled to an LC tank of the VCO. The auxiliary varactor has a capacitance controlled by a temperature-dependant control voltage to minimize the overall change in VCO frequency with temperature. Techniques for generating the control voltage using digital and analog means are further disclosed.

    摘要翻译： 公开了用于补偿温度变化对压控振荡器（VCO）频率的影响的技术。 在一个实施例中，辅助变容二极管耦合到VCO的LC箱。 辅助变容二极管具有由温度依赖控制电压控制的电容，以最小化VCO频率随温度的总体变化。 进一步公开了使用数字和模拟装置产生控制电压的技术。

    FAST-SWITCHING LOW-NOISE CHARGE PUMP
    10.
    发明申请
    FAST-SWITCHING LOW-NOISE CHARGE PUMP 有权
    快速切换低噪声充电泵

    公开(公告)号：US20090121759A1

    公开(公告)日：2009-05-14

    申请号：US11953575

    申请日：2007-12-10

    申请人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    发明人： Shen Wang ,  Sang-Oh Lee ,  Jeongsik Yang

    IPC分类号： G05F1/10 ,  H03L7/06

    CPC分类号： H03L7/0896 ,  H03L7/18

    摘要： In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.

    摘要翻译： 在本发明的一个实施例中，公开了一种用于电荷泵的方法。 该方法包括偏置多个晶体管; 切换一对主晶体管开关以通过偏置晶体管施加或去除输出端子上的净电荷; 并且当主晶体管开关断开时，接通辅助晶体管开关。 辅助晶体管开关导通时，为主晶体管开关和偏置晶体管之间的节点提供辅助均衡通路。 辅助均衡路径均衡中间节点之间的电压，以快速关闭偏置晶体管，并降低电荷泵输出端子上的噪声。