公开(公告)号：US20120306551A1

公开(公告)日：2012-12-06

申请号：US13482948

申请日：2012-05-29

申请人： Yong Hwan MOON ,  Young Soo RYU ,  Jae Ryun SHIM ,  Chul Soo JEONG ,  Sang Ho KIM

发明人： Yong Hwan MOON ,  Young Soo RYU ,  Jae Ryun SHIM ,  Chul Soo JEONG ,  Sang Ho KIM

IPC分类号： H03L7/08 ,  H03L7/00

CPC分类号： H03L7/0814

摘要： The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

摘要翻译： 本发明涉及一种假锁防止电路和方法，用于在DLL中发生错误锁定时使延迟锁定环（DLL）逃避诸如谐波锁定或卡锁的假锁，以及使用 一样。 该假锁防止电路包括配置成检测谐波锁定的谐波锁定检测器和被配置为检测卡锁的卡锁锁定检测器。 谐波锁定检测器包括被配置为对多个延迟时钟进行采样的多个触发器和逻辑单元。 谐波锁定检测器将参考时钟信号与多个延迟的时钟信号进行比较，并且检测正边缘是否偏离参考时钟信号的一个周期。