公开(公告)号：US08659329B2

公开(公告)日：2014-02-25

申请号：US13357224

申请日：2012-01-24

申请人： Yong Hwan Moon ,  Jun Ho Kim ,  Jae Ryun Shim ,  Chul Soo Jeong ,  Sang Ho Kim

发明人： Yong Hwan Moon ,  Jun Ho Kim ,  Jae Ryun Shim ,  Chul Soo Jeong ,  Sang Ho Kim

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K17/162 ,  H03K5/1515 ,  H04L25/03343

摘要： Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

摘要翻译： 提供了一种预加重电路，其响应于通过差分输入信号的逻辑运算产生的第一至第四预加重控制信号，将预加重输出电流发送到输出驱动器的输出节点。 预加重电路包括：第一预加重电路，其在第一电压和第二电压之间的范围内被驱动，并且被配置为响应于第一和第二预加重控制信号产生第一预加重输出电流并输出 生成的第一预加重输出电流到输出驱动器的第一输出节点; 以及第二预加重电路，其在所述第一电压和所述第二电压之间的范围内被驱动，并被配置为响应于所述第三和第四预加重控制信号产生第二预加重输出电流，并输出所生成的第二预加重 将输出电流输出到输出驱动器的第二输出节点。

公开(公告)号：US08698527B2

公开(公告)日：2014-04-15

申请号：US13482948

申请日：2012-05-29

申请人： Yong Hwan Moon ,  Young Soo Ryu ,  Jae Ryun Shim ,  Chul Soo Jeong ,  Sang Ho Kim

发明人： Yong Hwan Moon ,  Young Soo Ryu ,  Jae Ryun Shim ,  Chul Soo Jeong ,  Sang Ho Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal.

摘要翻译： 本发明涉及一种假锁防止电路和方法，用于在DLL中发生错误锁定时使延迟锁定环（DLL）逃避诸如谐波锁定或卡锁的假锁，以及使用 一样。 该假锁防止电路包括配置成检测谐波锁定的谐波锁定检测器和被配置为检测卡锁的卡锁锁定检测器。 谐波锁定检测器包括被配置为对多个延迟时钟进行采样的多个触发器和逻辑单元。 谐波锁定检测器将参考时钟信号与多个延迟的时钟信号进行比较，并且检测正边缘是否偏离参考时钟信号的一个周期。