公开(公告)号：US20210042274A1

公开(公告)日：2021-02-11

申请号：US17078865

申请日：2020-10-23

Applicant: Yong Jae LEE

Inventor： Yong Jae LEE

IPC: G06F16/21 ,  G06F16/23 ,  G06F16/955 ,  G06F16/93 ,  G06F16/28

Abstract: The present invention relates to a management system, a search method, and a browsing method of a unified data object using a tag object. A unified data object management system and method may efficiently access and manage the data object by storing and managing the unified data objects including a file, non-file data, or dynamic data on the basis of the tag object and then providing a search result based on the tag object when a search command is entered by a user.

公开(公告)号：US20110292020A1

公开(公告)日：2011-12-01

申请号：US13149388

申请日：2011-05-31

Applicant: Yong Jae LEE

Inventor： Yong Jae LEE

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G3/20 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2370/08

Abstract: A display device and method are provided. The display device includes a timing controller configured to insert a clock between data and transmit the data in which the clock has been inserted, transmission lines configured to transfer the data in which the clock has been inserted, and data driver integrated circuits (ICs) configured to receive the data in which the clock has been inserted, separate the clock from the data, and drive data lines of a liquid crystal panel on the basis of the clock and the data. The timing controller includes a phase-locked loop (PLL) including an oscillator and an inductor-capacitor (LC) resonant circuit, and a reset signal generator configured to generate a reset signal causing the PLL to start coarse frequency tuning when initial power is applied or a frequency of an applied input clock changes.

Abstract translation: 提供了一种显示装置和方法。 显示装置包括定时控制器，其被配置为在数据之间插入时钟并发送其中已经插入时钟的数据，配置成传送其中插入时钟的数据的传输线以及配置的数据驱动器集成电路（IC） 为了接收插入时钟的数据，将时钟与数据分开，并根据时钟和数据驱动液晶面板的数据线。 定时控制器包括一个包括一个振荡器和一个电感 - 电容（LC）谐振电路的锁相环（PLL），以及一个复位信号发生器，被配置为产生复位信号，使复位信号在初始电源被施加时使PLL开始粗调频率调谐 或施加的输入时钟的频率变化。

公开(公告)号：US20160132536A1

公开(公告)日：2016-05-12

申请号：US14897355

申请日：2014-06-05

Applicant: Yong Jae LEE

Inventor： Yong Jae LEE

IPC: G06F17/30

CPC classification number: G06F16/21 ,  G06F16/23 ,  G06F16/289 ,  G06F16/93 ,  G06F16/9558 ,  G06F16/9566

Abstract: The present invention relates to a management system, a search method, and a browsing method of a unified data object using a tag object. A unified data object management system and method may efficiently access and manage the data object by storing and managing the unified data objects including a file, non-file data, or dynamic data on the basis of the tag object and then providing a search result based on the tag object when a search command is entered by a user.

Abstract translation: 本发明涉及使用标签对象的统一数据对象的管理系统，搜索方法和浏览方法。 统一的数据对象管理系统和方法可以通过基于标签对象存储和管理包括文件，非文件数据或动态数据的统一数据对象，然后提供基于搜索结果的方式来有效地访问和管理数据对象 在用户输入搜索命令时在标签对象上。

公开(公告)号：US20110292011A1

公开(公告)日：2011-12-01

申请号：US13110523

申请日：2011-05-18

Applicant: Yong Jae LEE

Inventor： Yong Jae LEE

IPC: G09G3/36 ,  G09G5/00 ,  H03L7/08

CPC classification number: G09G3/3611 ,  G09G2370/08 ,  H03J2200/10 ,  H03L7/095 ,  H03L7/185

Abstract: Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.

Abstract translation: 提供了接收输入时钟并产生时钟的锁相环（PLL），使用PLL的显示器以及使用PLL来产生时钟的定时控制器的方法。 显示器包括定时控制器，其被配置为使用PLL生成第一时钟，将第一时钟插入到数据中，并且发送插入有第一时钟的数据，被配置为传送插入有第一时钟的数据的传输线， 以及被配置为接收插入有第一时钟的数据的数据驱动器集成电路（IC），将第一时钟与数据分开，并且基于第一时钟和数据驱动液晶面板的数据线。 PLL包括相位检测器，被配置为产生对应于输入时钟和第一时钟之间的相位差的DC误差，多个压控振荡器（VCO），VCO选择器，被配置为选择具有频率工作范围的VCO ，其是从VCO的最高振荡频率到最低振荡频率的范围，包括参考DC误差从多个VCO中的第一时钟的频率，以及连接的电感器/电容器（LC）谐振电路 所选择的VCO包括多个固定电容器，并被配置为对所选择的VCO进行粗略的频率调谐。

公开(公告)号：US20110140797A1

公开(公告)日：2011-06-16

申请号：US12964172

申请日：2010-12-09

Applicant: Yong Jae LEE

Inventor： Yong Jae LEE

IPC: H03B5/18

CPC classification number: H03B5/1847

Abstract: Provided is a signal generator. The signal generator includes an insulating substrate, a chip disposed on the insulating substrate and including an oscillator including a capacitance element determining a resonant frequency signal, and a plurality of conductive lines disposed on the same surface of the insulating substrate to be spaced apart from each other. At least one of the plurality of conductive lines is electrically connected with the oscillator and provides an inductance element determining the resonant frequency signal to the oscillator.

Abstract translation: 提供了一种信号发生器。 信号发生器包括绝缘衬底，设置在绝缘衬底上的芯片，并且包括：振荡器，其包括确定谐振频率信号的电容元件;以及多个导线，设置在绝缘衬底的与每个绝缘衬底相同的表面上 其他。 多个导线中的至少一个与振荡器电连接，并提供确定谐振频率信号给振荡器的电感元件。