公开(公告)号：US07352351B2

公开(公告)日：2008-04-01

申请号：US10789987

申请日：2004-03-02

申请人： Yong-Ho Jang ,  Kyung-Eon Lee

发明人： Yong-Ho Jang ,  Kyung-Eon Lee

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3611 ,  G09G2310/02 ,  G09G2320/02

摘要： A liquid crystal display device includes a liquid crystal panel having a pixel region, a graphic interface unit generating a first data enable signal having first and second time intervals, a signal modulating unit generating a second data enable signal by using the first data enable signal, the second data enable signal having third and fourth time intervals, and a timing controller generating the data signals by using the second data enable signal, wherein data signals are not input to the pixel region during the third time interval and are input to the pixel region during the fourth time interval, and the forth time interval is shorter than the second time interval.

摘要翻译： 一种液晶显示装置，包括具有像素区域的液晶面板，具有第一和第二时间间隔的产生第一数据使能信号的图形接口单元，通过使用第一数据使能信号产生第二数据使能信号的信号调制单元， 具有第三和第四时间间隔的第二数据使能信号，以及通过使用第二数据使能信号产生数据信号的定时控制器，其中数据信号在第三时间间隔期间不输入到像素区域并被输入到像素区域 并且第四时间间隔比第二时间间隔短。

公开(公告)号：US08633888B2

公开(公告)日：2014-01-21

申请号：US12647085

申请日：2009-12-24

申请人： Binn Kim ,  Yong-Ho Jang

发明人： Binn Kim ,  Yong-Ho Jang

IPC分类号： G09G3/36

CPC分类号： G09G3/344 ,  G09G2310/0267 ,  G09G2330/04 ,  G11C19/28

摘要： A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal.

摘要翻译： 公开了能够使峰值电压最小化的移位寄存器。 移位寄存器包括多个级，每个级包括多个节点，扫描脉冲输出单元根据节点处的电压控制，用于输出扫描脉冲并通过扫描输出端将其提供给相应的栅极线;进位脉冲 输出单元根据节点处的电压控制，用于输出进位脉冲，并通过进位输出端将其提供给上游级和下游级;节点控制器，用于响应于来自所述进位脉冲的进位脉冲控制所述节点的电压状态 上游级和来自下游级的进位脉冲，以及连接到多个时钟传输线中的任一个的放电单元和用于放电扫描输出端的尖峰电压的扫描输出端。

公开(公告)号：US20050156859A1

公开(公告)日：2005-07-21

申请号：US11020184

申请日：2004-12-27

申请人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/20 ,  G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3674 ,  G09G2300/08 ,  G09G2310/0267 ,  G11C19/00 ,  G11C19/184 ,  G11C19/28

摘要： A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.

摘要翻译： 用于平板显示装置的驱动电路包括产生m相循环使能控制时钟和n相循环形式生成时钟的第一和第二产生单元; 以及多个移位寄存器级，通过使用m相循环使能控制时钟和n相循环形式生成时钟来产生输出信号。 每个移位寄存器级包括接收m相循环使能控制时钟的输入端; 第一和第二节点分别使用m相循环启用控制时钟输出第一和第二信号; 连接到第一节点并接收n相循环形式的第一晶体管生成时钟; 连接到第二节点和第一晶体管的第二晶体管; 以及第一和第二晶体管之间的输出端子，并输出输出信号之一。

公开(公告)号：US08515001B2

公开(公告)日：2013-08-20

申请号：US13333465

申请日：2011-12-21

申请人： Yong-Ho Jang ,  Seung-Chan Choi

发明人： Yong-Ho Jang ,  Seung-Chan Choi

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3688 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/00

摘要： Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

公开(公告)号：US20100214279A1

公开(公告)日：2010-08-26

申请号：US12647085

申请日：2009-12-24

申请人： Binn Kim ,  Yong-Ho Jang

发明人： Binn Kim ,  Yong-Ho Jang

IPC分类号： G06F3/038

CPC分类号： G09G3/344 ,  G09G2310/0267 ,  G09G2330/04 ,  G11C19/28

摘要： A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal.

摘要翻译： 公开了能够使峰值电压最小化的移位寄存器。 移位寄存器包括多个级，每个级包括多个节点，扫描脉冲输出单元根据节点处的电压控制，用于输出扫描脉冲并通过扫描输出端将其提供给相应的栅极线;进位脉冲 输出单元根据节点处的电压控制，用于输出进位脉冲，并通过进位输出端将其提供给上游级和下游级;节点控制器，用于响应于来自所述进位脉冲的进位脉冲控制所述节点的电压状态 上游级和来自下游级的进位脉冲，以及连接到多个时钟传输线中的任一个的放电单元和用于放电扫描输出端的尖峰电压的扫描输出端。

公开(公告)号：US07349519B2

公开(公告)日：2008-03-25

申请号：US11171562

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Soo-Young Yoon

IPC分类号： G11C19/00

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G11C19/00 ,  G11C19/28

摘要： A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

摘要翻译： 输入移位寄存器结构，其包括用于顺序地输出电压作为时钟信号的移位寄存器和起始电压，以及连接到移位寄存器的清除器装置，用于消除起始电压内的噪声。 清洁装置是用于将时钟信号输入到门并将从移位寄存器输出的信号输入到源的晶体管。

公开(公告)号：US08604858B2

公开(公告)日：2013-12-10

申请号：US13402017

申请日：2012-02-22

申请人： Yong-Ho Jang ,  Seung-Chan Choi

发明人： Yong-Ho Jang ,  Seung-Chan Choi

IPC分类号： G06F1/04 ,  H03K3/00

CPC分类号： G09G3/3677 ,  G09G2320/0219 ,  G11C19/28

摘要： A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses.

摘要翻译： 栅极驱动电路包括用于输出具有不同相位的n个输出控制时钟脉冲的第一时钟发生器; 第二时钟发生器，用于产生具有不同相位的m * n个输出时钟脉冲并且在其高周期中彼此​​部分地重叠，以排列相序的m * n个输出时钟脉冲，以便将m * n个输出时钟脉冲排列 以n为单位的相位顺序产生m组，每组具有n个输出时钟脉冲，并输出m * n个输出时钟脉冲，使得输出时钟脉冲的上升沿具有第k个相位序列 每个组中包括的n个输出控制时钟脉冲中具有第k个相位序列的输出控制时钟脉冲的高周期; 以及顺序地输出多个扫描脉冲的移位寄存器。

公开(公告)号：US08558601B2

公开(公告)日：2013-10-15

申请号：US13541904

申请日：2012-07-05

申请人： Yong-Ho Jang ,  Seung-Chan Choi ,  Jae-Yong You ,  Woo-Seok Choi

发明人： Yong-Ho Jang ,  Seung-Chan Choi ,  Jae-Yong You ,  Woo-Seok Choi

IPC分类号： G04F1/04 ,  H03K3/00

CPC分类号： G09G3/3677 ,  G09G2310/0286

摘要： Disclosed herein is a gate driving circuit including a first clock generator to sequentially output n output clock pulses, a second clock generator to sequentially output n output control clock pulses, and a shift register to receive the n output clock pulses and the n output control clock pulses and to sequentially output a plurality of scan pulses, wherein high sections of k-th to (k+s)-th output clock pulses output during adjacent periods overlap with one another, a k-th output control clock pulse rises before the k-th output clock pulse, the k-th output control clock pulse falls before a (k−a)-th output clock pulse, a high section of the output control clock pulses does not overlap with that of the k-th output clock pulse, and a (k+b)-th output clock pulse falls during the high section of the output control clock pulses not overlapping with that of the k-th output clock pulse.

摘要翻译： 本文公开了一种栅极驱动电路，其包括顺序地输出n个输出时钟脉冲的第一时钟发生器，用于顺序地输出n个输出控制时钟脉冲的第二时钟发生器和用于接收n个输出时钟脉冲和n个输出控制时钟的移位寄存器 并且顺序地输出多个扫描脉冲，其中在相邻周期期间输出的第k个到第（k + s）个输出时钟脉冲的高部分彼此重叠，第k个输出控制时钟脉冲在k 第k个输出时钟脉冲，第k个输出控制时钟脉冲落在（ka）输出时钟脉冲之前，输出控制时钟脉冲的高部分与第k个输出时钟脉冲的高部分不重叠， 在输出控制时钟脉冲的高部分不与第k个输出时钟脉冲重叠的第（k + b）个输出时钟脉冲下降。

公开(公告)号：US08422621B2

公开(公告)日：2013-04-16

申请号：US13339239

申请日：2011-12-28

申请人： Yong-Ho Jang ,  Seung-Chan Choi ,  Jae-Yong You ,  Woo-Seok Choi

发明人： Yong-Ho Jang ,  Seung-Chan Choi ,  Jae-Yong You ,  Woo-Seok Choi

IPC分类号： G11C19/00

CPC分类号： G11C19/00 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

摘要翻译： 提供了一种移位寄存器，其中防止电荷从设定节点处的电压泄漏以稳定级的输出。 移位寄存器包括用于顺序地输出扫描脉冲的级。 第n个阶段包括用于控制节点处的电压的节点控制器，以及用于根据节点处的电压输出扫描脉冲中的相应一个扫描脉冲和第一放电电压中的任何一个的输出单元。 节点包括设置和重置节点。 第n级的节点控制器包括由提供给复位节点的电压控制的第一开关装置，用于向设定节点提供第二放电电压;以及逆变器电路，由提供给设定节点的电压控制， 充电电压和第三放电电压到复位节点。

公开(公告)号：US08049704B2

公开(公告)日：2011-11-01

申请号：US11173168

申请日：2005-06-30

申请人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

发明人： Yong-Ho Jang ,  Binn Kim ,  Su-Hwan Moon ,  Nam-Wook Cho ,  Soo-Young Yoon

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0205 ,  G09G2310/0251 ,  G09G2310/08

摘要： A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

摘要翻译： 液晶显示器（LCD）装置包括具有由多个栅极线和数据线限定的多个像素区域的液晶面板，与薄膜晶体管相关联的每个像素区域，具有非晶半导体的栅极驱动单元和一体的 形成有能够向位于像素区域内的薄膜晶体管的导通时间长的脉冲宽度的栅极线发送扫描信号的液晶面板，以及连接到能够发送的数据线的数据驱动单元 到数据线的图像信号。