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    FLASH MEMORY DEVICE CONFIGURED TO REDUCE COMMON SOURCE LINE NOISE, METHODS OF OPERATING SAME, AND MEMORY SYSTEM INCORPORATING SAME
    1.
    发明申请
    FLASH MEMORY DEVICE CONFIGURED TO REDUCE COMMON SOURCE LINE NOISE, METHODS OF OPERATING SAME, AND MEMORY SYSTEM INCORPORATING SAME 有权
    闪存存储器件被配置为减少通用信号线噪声，操作方法和与其同时存储的系统

    公开(公告)号：US20110058427A1

    公开(公告)日：2011-03-10

    申请号：US12838584

    申请日：2010-07-19

    申请人： Yoon-Hee CHOI ,  Ki tae PARK ,  Bo Geun KIM

    发明人： Yoon-Hee CHOI ,  Ki tae PARK ,  Bo Geun KIM

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3468 ,  G11C16/0483 ,  G11C16/10

    摘要： A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.

    摘要翻译： 闪存器件包括连接在位线和公共源极线之间的存储器单元，连接到存储器单元的字线，连接到公共源极线（CSL）的公共源极线反馈电路，以检测公共源极的电压电平 线路和CSL反馈控制逻辑，其配置成在所述存储器单元的感测操作期间基于所述检测到的所述CSL的电压电平来将所选择的字线或所选择的位线的电压电平控制为基本上恒定的值。