公开(公告)号：US20110058427A1

公开(公告)日：2011-03-10

申请号：US12838584

申请日：2010-07-19

申请人： Yoon-Hee CHOI ,  Ki tae PARK ,  Bo Geun KIM

发明人： Yoon-Hee CHOI ,  Ki tae PARK ,  Bo Geun KIM

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3468 ,  G11C16/0483 ,  G11C16/10

摘要： A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL.

摘要翻译： 闪存器件包括连接在位线和公共源极线之间的存储器单元，连接到存储器单元的字线，连接到公共源极线（CSL）的公共源极线反馈电路，以检测公共源极的电压电平 线路和CSL反馈控制逻辑，其配置成在所述存储器单元的感测操作期间基于所述检测到的所述CSL的电压电平来将所选择的字线或所选择的位线的电压电平控制为基本上恒定的值。

公开(公告)号：US20110280070A1

公开(公告)日：2011-11-17

申请号：US13073029

申请日：2011-03-28

申请人： Jong-Young KIM ,  Ki Tae PARK ,  Bo Geun KIM

发明人： Jong-Young KIM ,  Ki Tae PARK ,  Bo Geun KIM

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5628

摘要： A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession.

摘要翻译： 非易失性存储器件包括存储单元阵列，页缓冲器和控制电路。 存储单元阵列包括配置为存储硬判决数据位的多电平单元。 页面缓冲器被配置为响应于在第一读取操作期间施加到所选择的字线的第一读取电压，感测多电平单元中的每一个是否呈现接通电池状态或关闭电池状态，以设置第一软判定 数据位，并且响应于在第二读取操作中施加到所选择的字线的第二读取电压来感测来自所述多电平单元中的每一个的一个或多个硬判决数据位。 控制电路被配置为控制连续执行的第一读取操作和第二读取操作。

公开(公告)号：US20110194346A1

公开(公告)日：2011-08-11

申请号：US12963867

申请日：2010-12-09

申请人： Sang Yong YOON ,  Ki Tae PARK ,  Moo Sung KIM ,  Bo Geun KIM ,  Hyun jun YOON

发明人： Sang Yong YOON ,  Ki Tae PARK ,  Moo Sung KIM ,  Bo Geun KIM ,  Hyun jun YOON

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/3459 ,  G11C11/56 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/3454

摘要： A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state.

摘要翻译： 一种对闪速存储器件进行编程的方法包括编程所选择的存储器单元，执行验证操作以确定所选择的存储器单元是否已经达到目标程序状态，以及基于与检测相关联的编程特性来确定验证操作的起始点 在编程初始程序状态期间的通过位。

公开(公告)号：US20110205817A1

公开(公告)日：2011-08-25

申请号：US13027439

申请日：2011-02-15

申请人： Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

发明人： Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5648

摘要： A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy.

摘要翻译： 存储器系统包括多位存储器件和控制多位存储器件的存储器控​​制器。 存储器系统确定所请求的程序操作是随机程序操作还是顺序程序操作。 在所请求的程序操作是随机程序操作的情况下，存储器控制器控制多位存储器件根据精细程序关闭策略或精细程序打开策略执行操作。

公开(公告)号：US20110080791A1

公开(公告)日：2011-04-07

申请号：US12793007

申请日：2010-06-03

申请人： Bo Geun KIM ,  Kitae PARK

发明人： Bo Geun KIM ,  Kitae PARK

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C7/1048 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops.

摘要翻译： 非易失性存储器件的编程方法包括通过在某些程序循环的程序验证操作期间执行具有位线预充电的多个程序循环来编程存储器单元，并且在某些程序循环的程序验证操作期间激活位线预充电。