公开(公告)号：US5699264A

公开(公告)日：1997-12-16

申请号：US633315

申请日：1996-04-17

申请人： Yoshiki Nakamura ,  Hirofumi Yamamoto ,  Terutoshi Yamasaki

发明人： Yoshiki Nakamura ,  Hirofumi Yamamoto ,  Terutoshi Yamasaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In a semiconductor circuit design verifying apparatus, a parasitic device retrieving part retrieves a parasitic device for a signal line connecting first stage active devices to a next stage active device. A time constant computing device computes a time constant between each first stage active device and the next stage active device including the parasitic device for the signal line between the first stage active devices and the next stage active device. An output data generating device outputs the time constant and information associated with the time constant to a user.

摘要翻译： 在半导体电路设计验证装置中，寄生器件检索部分检索用于将第一级有源器件连接到下一级有源器件的信号线的寄生器件。 时间常数计算设备计算每个第一级有源器件和下一级有源器件之间的时间常数，其包括用于第一级有源器件与下一级有源器件之间的信号线的寄生器件。 输出数据生成装置将时间常数和与时间常数相关联的信息输出给用户。

公开(公告)号：US06965853B2

公开(公告)日：2005-11-15

申请号：US09773623

申请日：2001-02-02

申请人： Hiroyuki Kuzuma ,  Terutoshi Yamasaki

发明人： Hiroyuki Kuzuma ,  Terutoshi Yamasaki

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5022

摘要： A back annotation apparatus, which effectively carries out a back annotation, includes: a pre-layout simulation implementing part for detecting nodes of which the potential changes when a predetermined signal is applied to a logic circuit; a layout pattern verification implementing part for implementing a predetermined layout pattern verification for layout patterns of the logical circuit; a parasitic element extraction part connected to the pre-layout simulation implementing part which extracts parasitic elements from the nodes of which the potential changes; a net list generation part connected to the parasitic element extraction part for generating a net list which includes all the devices included in the layout pattern data and parasitic elements extracted in the parasitic element extraction part; and a post layout simulation implementing part connected to the net list generation part for implementing a post layout simulation by using the net list.

摘要翻译： 有效地执行反向注释的反向注释装置包括：预定布局模拟实现部分，用于检测当预定信号被施加到逻辑电路时电位改变的节点; 布局图案验证实现部件，用于对逻辑电路的布局图案进行预定的布局图案验证; 一个寄生元件提取部分，连接到预先布局模拟实现部分，该部分从电位变化的节点中提取寄生元件; 连接到寄生元件提取部分的网表生成部分，用于生成包括在布局图案数据中包括的所有装置和在寄生元件提取部分中提取的寄生元件的网表; 以及与网表生成部连接的后布局模拟实现部，通过使用网表实现后布局模拟。

公开(公告)号：US06427225B1

公开(公告)日：2002-07-30

申请号：US09239148

申请日：1999-01-28

申请人： Osamu Kitada ,  Terutoshi Yamasaki ,  Hironobu Taoka

发明人： Osamu Kitada ,  Terutoshi Yamasaki ,  Hironobu Taoka

IPC分类号： G06F1750

CPC分类号： G06F17/5081 ,  G03F1/36

摘要： A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.

摘要翻译： 根据图案形状，包括尺寸精度的半导体集成电路布局图以高精度有效地验证。 一种用于基于向量数据验证布图是否符合设计规则的布局验证方法，包括：参考矢量分类步骤，用于选择和分类参考矢量，所述参考矢量用作对应于侧面的矢量中的验证参考， 验证对象矢量分类步骤，用于选择和分类对应于所述边的矢量中的待验证对象矢量;以及验证步骤，用于验证在要被验证的所述待验证矢量之间的距离， 与参考矢量的方向对应。