公开(公告)号：US4811213A

公开(公告)日：1989-03-07

申请号：US918003

申请日：1986-10-14

申请人： Yoshio Takamine ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita ,  Shunsuke Miyamoto

发明人： Yoshio Takamine ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita ,  Shunsuke Miyamoto

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/347

CPC分类号： G06F15/8084

摘要： In response to the execution of a single loading instruction, the front half and the rear half of a designated vector may be stored in respective vector registers in a single processor operation. For this purpose, a data distribution circuit is interposed between a group of vector registers and a vector data storage for feeding the vector data read out from the storage to a first vector processor designated by an instruction without shifting and for shifting the respective components of the read-out vector data and feeding the shifted components to a second vector register designated by the instruction.

摘要翻译： 响应于单个加载指令的执行，指定向量的前半部分和后半部分可以在单个处理器操作中存储在相应的向量寄存器中。 为此，在一组向量寄存器和向量数据存储器之间插入数据分配电路，用于将从存储器读出的向量数据馈送到由指令指定的第一向量处理器，而不需要移位，并且用于将 读出向量数据并将移位的分量馈送到由指令指定的第二向量寄存器。

公开(公告)号：US5051941A

公开(公告)日：1991-09-24

申请号：US478511

申请日：1990-02-12

申请人： Yoshio Takamine ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Yoshio Takamine ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method of logic simulation for simulating operation of a logic circuit by using basic signal values corresponding to states of output signals of elements of the logic circuit to be simulated and expanded signal values including the basic signal values. The logic circuit to be simulated is divided into a portion to be simulated by using the basic signal values and the expanded signal values and a portion to be simulated by using the basic signal values without using the expanded signal values. The elements for which definition of calculation method for output signal values for the input signal values including the expanded signal values is not easy are included in the latter portion, and other elements are included in the former portion. A virtual signal conversion element for converting the expanded signal into the basic signal is provided at a position where a signal is sent from the former portion to the latter portion so that the expanded signal value outputted from the element of the former portion is converted into the basic signal value before it is sent to the element of the latter portion.

摘要翻译： 一种逻辑仿真方法，用于通过使用与要被仿真的逻辑电路的元件的输出信号的状态对应的基本信号值和包括基本信号值的扩展信号值来模拟逻辑电路的操作。 要模拟的逻辑电路通过使用基本信号值和扩展信号值以及通过使用基本信号值而不使用扩展信号值而要被仿真的部分来划分为要被模拟的部分。 对于包括扩展信号值的输入信号值的输出信号值的计算方法的定义不容易的元件包括在后一部分中，并且其它元件包括在前一部分中。 将扩展信号转换为基本信号的虚拟信号转换元件设置在信号从前一部分发送到后一部分的位置，使得从前一部分的元件输出的扩展信号值被转换为 基本信号值被发送到后一部分的元素之前。

公开(公告)号：US4899273A

公开(公告)日：1990-02-06

申请号：US940539

申请日：1986-12-10

申请人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/16 ,  G01R31/317 ,  G01R31/3173 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/31705 ,  G01R31/3173

摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

摘要翻译： 一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。 时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。 每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。 锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。 因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

公开(公告)号：US4933839A

公开(公告)日：1990-06-12

申请号：US79047

申请日：1987-07-29

申请人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Yoshio Takamine

发明人： Yoshiaki Kinoshita ,  Yoshiharu Kazama ,  Yoshio Takamine

IPC分类号： G06F7/00 ,  G06F7/02 ,  G06F7/76 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8053 ,  G06F7/02

摘要： A vector processor has a discriminator for determining in one machine cycle of an operation unit whether a bit pattern of elements of vector data meets a predetermined condition or not. An output of a register having a predetermined value loaded only into bits to be extracted from the vector data and each of the elements of the vector data are ANDed or ORed so that the bit pattern is determined. The operation and determination are sequentially carried out in one machine cycle.

摘要翻译： 矢量处理器具有用于在操作单元的一个机器周期中确定矢量数据的元素的位模式是否满足预定条件的鉴别器。 具有预定值的寄存器的输出仅被加载到从矢量数据提取的比特中，并且向量数据的每个元素进行“或”运算，以便确定比特模式。 操作和确定在一个机器周期中依次进行。

公开(公告)号：US5592655A

公开(公告)日：1997-01-07

申请号：US341115

申请日：1994-11-18

申请人： Yoshio Takamine ,  Kei Suzuki ,  Toshihiko Sugita

发明人： Yoshio Takamine ,  Kei Suzuki ,  Toshihiko Sugita

IPC分类号： G06F11/25 ,  G06F11/26 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022

摘要： For simulation evaluation of combinational logic, changes in input signals are reserved for events occurring with respect to every element of the combinational logic circuit or of a partial circuit within the logic circuit according to demand timing. To inhibit wasteful processes, when the output value of a pertinent element or partial circuit is required by an element included in another partial circuit, i.e. when a demand has been sensed, only then are the events which occurred before evaluation.

摘要翻译： 对于组合逻辑的模拟评估，输入信号的变化被保留用于根据需求定时相对于组合逻辑电路的每个元件或逻辑电路内的部分电路发生的事件。 为了抑制浪费的处理，当包括在另一部分电路中的元件需要相关元件或部分电路的输出值时，即当已经感测到需求时，才是在评估之前发生的事件。

公开(公告)号：US06536031B2

公开(公告)日：2003-03-18

申请号：US09906756

申请日：2001-07-18

申请人： Masaki Ito ,  Yoshio Takamine

发明人： Masaki Ito ,  Yoshio Takamine

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A method for automatically generating a behavior model description of a circuit that is used with a simulator and a logic verification apparatus. An interface description defining the state transition of input/output signals of a logic circuit module at clock cycle accuracy and a functional description defining the processing function of signals or data of the logic circuit module as a program function are read, and a logic behavior model description of a circuit defining in-circuit behavior and a state transition of input/output signal at clock cycle accuracy is automatically generated.

公开(公告)号：US5245550A

公开(公告)日：1993-09-14

申请号：US820995

申请日：1992-01-15

申请人： Yoshio Miki ,  Kei Suzuki ,  Yoshio Takamine

发明人： Yoshio Miki ,  Kei Suzuki ,  Yoshio Takamine

IPC分类号： H01L21/82 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring route is determined between terminals on an integrated circuit on the basis of information concerning the terminals and areas of the integrated circuit through which a wire can be routed. A mesh memory holds information of mesh points of a wiring area partitioned in a mesh-like pattern. A wavefront memory holds information concerning mesh points constituting the leads of searching point arrays. An expansion point extracting unit selects a source point from the mesh points for a succeeding search from the leading mesh points on the basis of costs. Addresses and costs for mesh points neighboring the source point are calculated. A searching point register holds information concerning the mesh points obtained through the calculation. A determination is made of whether or not the mesh points placed in the searching point register can be searched, and if so they are written to the mesh memory. Duplicate information stored in the searching point register is eliminated. It is then determined whether or not the mesh points corresponding to the terminals to be wired are contained in the searching point register. If so, the wiring route is determined and the process concluded.

摘要翻译： 在集成电路的端子之间根据关于可以布线的集成电路的端子和区域的信息确定布线路线。 网格存储器保持以网状图案划分的布线区域的网格点的信息。 波前存储器保存关于构成搜索点阵列的引线的网点的信息。 扩展点提取单元根据成本从前述网格点从网格点中选择来自后续搜索的源点。 计算与源点相邻的网格点的地址和成本。 搜索点寄存器保存关于通过计算获得的网格点的信息。 确定是否可以搜索放置在搜索点寄存器中的网格点，如果是，则将其写入网格存储器。 消除了存储在搜索点寄存器中的重复信息。 然后，确定与要接线的终端相对应的网格点是否包含在搜索点寄存器中。 如果是这样，则确定布线路线，结束处理。

公开(公告)号：US20050047260A1

公开(公告)日：2005-03-03

申请号：US10892298

申请日：2004-07-16

申请人： Kaname Yamasaki ,  Yoshio Takamine

发明人： Kaname Yamasaki ,  Yoshio Takamine

IPC分类号： G01R31/28 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/20

CPC分类号： G11C29/20 ,  G11C2029/3602

摘要： Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.

摘要翻译： 测试功能通过采用自检部分进行扩展，通过添加自检部分来减小电路规模。 半导体集成电路包括包括多个存储体并通过指定存储体地址，X地址和Y地址进行访问的存储器，以及响应于命令测试存储器的自检部件。 自检部分具有覆盖在X地址，Y地址和银行地址的更新中不同的多个寻址模式的地址计数器。 提供的各种寻址模式扩展了基于BIST的测试功能。

公开(公告)号：US4833619A

公开(公告)日：1989-05-23

申请号：US945946

申请日：1986-12-24

申请人： Tsuguo Shimizu ,  Yoshio Takamine

发明人： Tsuguo Shimizu ,  Yoshio Takamine

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Herein disclosed is an automatic design system for automatically generating a data structure, which is only implicitly expressed by a logic specification description, by deriving, in case a logic system has data structures of similar constructions, one data structure from the structure description and transfer behavior description of the other data structure.

摘要翻译： 这里公开了一种自动设计系统，用于通过在逻辑系统具有类似结构的数据结构的情况下导出来自结构描述和传输行为的一个数据结构来自动生成仅由逻辑规范描述隐含地表达的数据结构 其他数据结构的描述。

公开(公告)号：US20090063913A1

公开(公告)日：2009-03-05

申请号：US12073885

申请日：2008-03-11

申请人： Kaname Yamasaki ,  Yoshio Takamine

发明人： Kaname Yamasaki ,  Yoshio Takamine

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/20 ,  G11C2029/3602

摘要： Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.

摘要翻译： 通过采用测试部件扩展测试功能，通过添加测试部件来减小电路规模的增加。 半导体集成电路包括包括多个存储体的存储器，并且通过指定存储体地址，X地址和Y地址以及响应于命令来测试存储器的自检部件被访问。 自检部分具有地址计数器，覆盖了如何更新X地址，Y地址和银行地址的不同的寻址模式。 为测试提供的各种寻址模式有助于扩展基于BIST的测试功能。 由于自检部分具有对应于多个测试模式的多个测试序列器，所以与需要用于存储程序的存储器的程序控制的通用定序器相比，可以容易地减少半导体集成电路的面积。