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公开(公告)号：US5835505A
公开(公告)日：1998-11-10
申请号：US843581
申请日：1997-04-16
申请人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
发明人： Yoshito Nishimichi , Satoshi Ogura , Shinji Ozaki , Seiji Tokunoh , Akira Miyoshi , Hiroaki Yamamoto , Yoshiaki Kasuga
CPC分类号： G06F11/3648
摘要： A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.
摘要翻译： 半导体集成电路包括实现半导体集成电路的功能的至少一部分的功能块。 功能块包括多个基本单元和多个终端单元。 多个终端单元中的每一个具有用于中介另一半导体集成电路与多个基本单元中的一个之间的通信的连接器。
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公开(公告)号：US5754813A
公开(公告)日：1998-05-19
申请号：US811663
申请日：1997-03-05
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译： 两个指令执行单元执行不同类型的指令。 提供两个指令选择电路。 两个指令总线耦合到具有预解码器和指令队列的指令备用单元。 指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。 指令获取控制电路检测任何指令执行单元尚未执行的指令。 这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。 作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。
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公开(公告)号：US5829021A
公开(公告)日：1998-10-27
申请号：US470933
申请日：1995-06-06
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3869
摘要： Two instruction execution units execute different types of instructions. Two instruction selection circuits are provided. Two instruction buses are coupled to an instruction standby unit having predecoders and an instruction queue. The instruction standby unit is connected by two wait instruction buses to the input sides of the instruction selection circuits. An instruction fetch control circuit detects an instruction that has not been executed by any of the instruction execution units. Such an unexecuted instruction waits in the instruction queue, thereafter being applied, together with its predecode result, to each instruction selection circuit to be selected at the next selection time. As a result of such arrangement, fast execution of different types of instructions in parallel is accomplished.
摘要翻译： 两个指令执行单元执行不同类型的指令。 提供两个指令选择电路。 两个指令总线耦合到具有预解码器和指令队列的指令备用单元。 指令备用单元通过两条等待指令总线连接到指令选择电路的输入侧。 指令获取控制电路检测任何指令执行单元尚未执行的指令。 这种未执行的指令在指令队列中等待，然后与其预解码结果一起应用于在下一个选择时间被选择的每个指令选择电路。 作为这种安排的结果，可以实现并行执行不同类型指令的快速执行。
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4.发明授权Apparatus for pipelining sequential instructions in synchronism with an operation clock 失效用于与操作时钟同步地进行顺序指令的装置
公开(公告)号：US6161171A
公开(公告)日：2000-12-12
申请号：US105212
申请日：1998-06-26
申请人： Toru Morikawa , Nobuo Higaki , Shinji Ozaki , Keisuke Kaneko , Satoshi Ogura , Masato Suzuki
发明人： Toru Morikawa , Nobuo Higaki , Shinji Ozaki , Keisuke Kaneko , Satoshi Ogura , Masato Suzuki
CPC分类号： G06F9/3867 , G06F12/0855
摘要： A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.
摘要翻译： 需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令，然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令 设置，应加入管道处理。 在提供具有较高频率的操作时钟的高速模式中，控制指令执行电路和数据存储器之间的数据高速缓冲存储器，以将数据字提供给指令执行的WB（回写）级 电路相对于与第一指令相关联的输入地址在两个周期内。 为了执行第二指令，数据字从WB级提供给指令执行电路的EX（操作执行）级。 在提供具有较低频率的操作时钟的低速模式中，控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM（存储器访问）级 与第一条指令相关联。 为了执行第二条指令，将数据字从MEM级旁路到EX级。
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5.发明授权Pipeline processor capable of reducing branch hazards with small-scale circuit 失效管道处理器能够通过小规模电路降低分支危险公开(公告)号：US06189092B1
公开(公告)日：2001-02-13
申请号：US09099299
申请日：1998-06-18
申请人： Satoshi Ogura , Shinji Ozaki
发明人： Satoshi Ogura , Shinji Ozaki
IPC分类号： G06F938
摘要： A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.
摘要翻译： 处理器使用紧接在程序循环之前设置的分支目标信息寄存器指令和设置在程序循环结束的高速循环指令，高速执行程序循环。 当分支目标信息寄存器指令被指令解码器解码时，取出的指令缓冲器中的代码被发送到分支目标指令寄存器，并且解码指令计数器中的移位指针被发送到分支目标提取地址寄存器。 在由指令解码器解码高速循环指令并且分支条件满足之后，转移目标提取地址寄存器中的指针被发送到获取的指令计数器和解码的指令计数器，同时分支目标中的代码 指令寄存器被发送到解码指令缓冲器。 通过使用解码指令计数器中的移位指针，可以用小规模硬件有效地执行高速循环指令。
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公开(公告)号：US07155649B2
公开(公告)日：2006-12-26
申请号：US10722752
申请日：2003-11-26
申请人： Toshinobu Nakao , Shinji Ozaki , Tomohisa Sezaki
发明人： Toshinobu Nakao , Shinji Ozaki , Tomohisa Sezaki
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/31858 , G01R31/318594
摘要： A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n−1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.
摘要翻译： 扫描测试电路设置有具有n个扫描存储元件（n：整数，n> 1）的扫描链; 扫描时钟生成电路，其能够控制用于将数据移位到第一至第（n-1）个扫描存储元件中的第一时钟的频率，以及用于将数据移位到第二时钟的频率 第n扫描存储元件，并且彼此独立地执行实际操作; 以及扫描选择内部信号产生电路，用于产生与第二时钟同步的扫描选择内部信号。
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7.发明授权Dual record/read head video recording and playback apparatus with fade-in function 失效具有淡入功能的双记录/读头视频录放设备
公开(公告)号：US4992891A
公开(公告)日：1991-02-12
申请号：US303749
申请日：1989-01-27
CPC分类号： H04N5/2621 , G11B27/032 , H04N5/265 , H04N5/782 , H04N9/793 , H04N9/80
摘要： A pair of recording heads are mounted on a rotary cylinder for recording a video signal in slanted tracks on magnetic tape. The recording heads are mounted in a common plane and each has a different azimuthal angle. A pair of reading heads are mounted on the same rotary cylinder for reading the video signal recorded on the magnetic tape. The reading heads are mounted in a plane offset from the plane of the recording heads and have azimuthal angles that match the azimuthal angles of the recording heads. A mixing circuit mixes a component of the video signal ready from the magnetic tape by one of the recording heads with a video signal from a video signal source to generate a mixed video signal. The mixed video signal is returned to one of the recording heads for recordation on the magnetic tape.
摘要翻译： 一对记录头安装在用于在磁带上的倾斜轨迹中记录视频信号的旋转圆筒上。 记录头安装在公共平面中，每个具有不同的方位角。 一对读取头安装在相同的旋转圆筒上，用于读取记录在磁带上的视频信号。 读取头安装在与记录头的平面偏移的平面中，并且具有与记录头的方位角匹配的方位角。 混合电路通过一个记录头将来自磁带的视频信号的分量与来自视频信号源的视频信号混合，以产生混合视频信号。 混合视频信号返回到一个记录头，用于在磁带上记录。
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公开(公告)号：US07084617B2
公开(公告)日：2006-08-01
申请号：US11094153
申请日：2005-03-31
申请人： Shinji Ozaki , Takashige Saitou
发明人： Shinji Ozaki , Takashige Saitou
IPC分类号： G01R33/00
CPC分类号： G01R15/202 , G01R15/207
摘要： An electric current sensor includes: a core having a ring shape and including a plurality of core pieces, which are laminated and integrated to provide the core; a magnetic gap disposed on a predetermined part of the core; a Hall element disposed in the magnetic gap; a body for accommodating the core and the Hall element; and a seal member for sealing the core and the Hall element into the body. Each core piece has a thin plate shape, and the core includes deformation preventing means for preventing a deformation of the magnetic gap.
摘要翻译： 电流传感器包括：具有环形并且包括多个芯片的芯体，其被层压并一体化以提供芯体; 设置在所述芯的预定部分上的磁隙; 设置在所述磁隙中的霍尔元件; 用于容纳所述芯体和所述霍尔元件的主体; 以及用于将芯体和霍尔元件密封到体内的密封构件。 每个芯片具有薄板形状，并且芯部包括用于防止磁隙变形的变形防止装置。
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公开(公告)号：US20050237049A1
公开(公告)日：2005-10-27
申请号：US11094153
申请日：2005-03-31
申请人： Shinji Ozaki , Takashige Saitou
发明人： Shinji Ozaki , Takashige Saitou
CPC分类号： G01R15/202 , G01R15/207
摘要： An electric current sensor includes: a core having a ring shape and including a plurality of core pieces, which are laminated and integrated to provide the core; a magnetic gap disposed on a predetermined part of the core; a Hall element disposed in the magnetic gap; a body for accommodating the core and the Hall element; and a seal member for sealing the core and the Hall element into the body. Each core piece has a thin plate shape, and the core includes deformation preventing means for preventing a deformation of the magnetic gap.
摘要翻译： 电流传感器包括：具有环形并且包括多个芯片的芯体，其被层压并一体化以提供芯体; 设置在所述芯的预定部分上的磁隙; 设置在所述磁隙中的霍尔元件; 用于容纳所述芯体和所述霍尔元件的主体; 以及用于将芯体和霍尔元件密封到体内的密封构件。 每个芯片具有薄板形状，并且芯部包括用于防止磁隙变形的变形防止装置。
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10.发明授权Control signal detection method with calibration error and subscriber unit therewith 失效具有校准误差的控制信号检测方法及其用户单元
公开(公告)号：US5657356A
公开(公告)日：1997-08-12
申请号：US670748
申请日：1996-06-21
申请人： Shinji Ozaki
发明人： Shinji Ozaki
CPC分类号： H04L25/062 , H04L1/24 , H04L27/20
摘要： In a control signal detection method, a calibration error value is obtained by obtaining the mean value of the received continuous (4.times.n) data, and the calibration error is compensated with respect to the received data by subtracting the obtained calibration error value from the received data, and the correlation value is obtained on the basis of the corrected received data, so that the control signal is detected. Therefore, it is able to compensate the calibration error with ease and to detect the control signal efficiently, with a simple construction.
摘要翻译： 在控制信号检测方法中，通过获得所接收的连续（4×n）数据的平均值来获得校准误差值，并且通过从接收到的数据中减去所获得的校准误差值来相对于接收数据补偿校准误差 ，并且基于校正的接收数据获得相关值，从而检测控制信号。 因此，能够以简单的结构容易地补偿校准误差并有效地检测控制信号。
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