公开(公告)号：US08232619B2

公开(公告)日：2012-07-31

申请号：US12836482

申请日：2010-07-14

申请人： Young Hee Yoon ,  Jun Gi Choi ,  Sang Hoon Shin

发明人： Young Hee Yoon ,  Jun Gi Choi ,  Sang Hoon Shin

IPC分类号： H01L23/52 ,  H01L23/34

CPC分类号： H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor integrated circuit. The semiconductor integrated circuit comprises: a pair of interconnections; a fuse connecting the pair of interconnections; and one or more heat dissipation patterns connecting the pair of interconnections and are disposed around the fuse.

摘要翻译： 提供了一种半导体集成电路。 半导体集成电路包括：一对互连; 连接该对互连的保险丝; 以及连接所述一对互连件的一个或多个散热图案，并且设置在保险丝周围。

公开(公告)号：US08053346B2

公开(公告)日：2011-11-08

申请号：US12109637

申请日：2008-04-25

申请人： Nam Gyu Ryu ,  Ho Ryong Kim ,  Won John Choi ,  Jae Hwan Kim ,  Seoung Hyun Kang ,  Young Hee Yoon

发明人： Nam Gyu Ryu ,  Ho Ryong Kim ,  Won John Choi ,  Jae Hwan Kim ,  Seoung Hyun Kang ,  Young Hee Yoon

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L27/088

CPC分类号： H01L27/0207 ,  Y10S438/926

摘要： A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

摘要翻译： 半导体器件中的栅极形成为具有保护栅极的伪栅极图案。 形成金属线以为半导体器件供电并传输信号。 半导体器件包括四耦合接收器型输入/输出缓冲器。 半导体器件形成有在有源区域上延伸的栅极线和位于有源区域外部的栅极焊盘。 栅极线和栅极焊盘相邻，使得栅极线和栅极焊盘的一侧形成一条线。 也可以应用虚拟门。 半导体器件包括向具有多个单元的块提供功率的第一金属线图案，向单元传输信号的第二金属线图案和沿纵向方向分割的虚拟金属线图案。