公开(公告)号：US08471616B2

公开(公告)日：2013-06-25

申请号：US13533001

申请日：2012-06-26

申请人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

发明人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

IPC分类号： H03L7/06

CPC分类号： H03K5/1565

摘要： A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

摘要翻译： 一种用于校正时钟信号的占空比的占空比校正电路。 占空比校正电路包括不对称缓冲器，其接收时钟信号并根据控制信号调整时钟信号的占空比; 时钟发生电路，连接到不对称缓冲器并检测时钟信号的占空比; 以及根据时钟信号的占空比产生控制信号的控制器。 将控制器的操作作为程序记录在计算机可读记录介质上。