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    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY
    1.
    发明申请
    VOLTAGE SCALING DEVICE OF SEMICONDUCTOR MEMORY 审中-公开
    半导体存储器的电压调节装置

    公开(公告)号：US20130094312A1

    公开(公告)日：2013-04-18

    申请号：US13584849

    申请日：2012-08-14

    申请人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    发明人： SOON-BOK JANG ,  JONG-UK SONG ,  YOUNG-WOOK KIM ,  HWA-SEOK OH

    IPC分类号： G11C7/00 ,  H01L35/00

    CPC分类号： G11C29/021 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/5002

    摘要： A voltage scaling device of a semiconductor memory device, the voltage scaling device including: a delay tester for determining the number of delay cells of a delay locked loop (DLL) required to cumulatively delay a clock signal having a constant frequency, and which is input to the DLL, by one clock period; a temperature sensor for measuring the temperature of the semiconductor memory device; and a voltage regulator for regulating a supply voltage of a voltage source which provides a chip voltage to the semiconductor memory device in response to the temperature measured by the temperature sensor and a locking value corresponding to the number of delay cells calculated by the delay tester.

    摘要翻译： 一种半导体存储器件的电压调节装置，所述电压缩放装置包括：延迟测试器，用于确定累积地延迟具有恒定频率的时钟信号所需的延迟锁定环（DLL）的延迟单元数量，并且其被输入 到DLL，一个时钟周期; 温度传感器，用于测量半导体存储器件的温度; 以及电压调节器，用于响应于由温度传感器测量的温度和对应于由延迟测试器计算的延迟单元的数量的锁定值，调节向半导体存储器件提供芯片电压的电压源的电源电压。

    Duty ratio correction circuit
    2.
    发明授权
    Duty ratio correction circuit 有权
    占空比校正电路

    公开(公告)号：US08471616B2

    公开(公告)日：2013-06-25

    申请号：US13533001

    申请日：2012-06-26

    申请人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

    发明人： Young-wook Kim ,  Soon-bok Jang ,  Jong-uk Song ,  Hwa-seok Oh ,  Sung-ha Kim

    IPC分类号： H03L7/06

    CPC分类号： H03K5/1565

    摘要： A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that is connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

    摘要翻译： 一种用于校正时钟信号的占空比的占空比校正电路。 占空比校正电路包括不对称缓冲器，其接收时钟信号并根据控制信号调整时钟信号的占空比; 时钟发生电路，连接到不对称缓冲器并检测时钟信号的占空比; 以及根据时钟信号的占空比产生控制信号的控制器。 将控制器的操作作为程序记录在计算机可读记录介质上。

    DUTY RATIO CORRECTION CIRCUIT
    4.
    发明申请
    DUTY RATIO CORRECTION CIRCUIT 有权
    占空比校正电路

    公开(公告)号：US20130015897A1

    公开(公告)日：2013-01-17

    申请号：US13533001

    申请日：2012-06-26

    申请人： Young-wook KIM ,  Soon-bok JANG ,  Jong-uk SONG ,  Hwa-seok OH ,  Sung-ha KIM

    发明人： Young-wook KIM ,  Soon-bok JANG ,  Jong-uk SONG ,  Hwa-seok OH ,  Sung-ha KIM

    IPC分类号： H03K3/017 ,  H03L7/08

    CPC分类号： H03K5/1565

    摘要： A duty ratio correction circuit for correcting a duty ratio of a clock signal. The duty ratio correction circuit includes an asymmetry buffer that receives a clock signal and adjusts a duty ratio of the clock signal in response to control signals; a clock generating circuit that i s connected to the asymmetry buffer and detects the duty ratio of the clock signal; and a controller that generates the control signals according to the duty ratio of the clock signal. An operation of the controller is recorded as a program on a computer-readable recording medium.

    摘要翻译： 一种用于校正时钟信号的占空比的占空比校正电路。 占空比校正电路包括不对称缓冲器，其接收时钟信号并根据控制信号调整时钟信号的占空比; 时钟发生电路，其连接到不对称缓冲器并检测时钟信号的占空比; 以及根据时钟信号的占空比产生控制信号的控制器。 将控制器的操作作为程序记录在计算机可读记录介质上。

    Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same
    7.
    发明授权
    Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same 有权
    补偿PCI Express和PCI Express物理层接收机的字节偏移的方法

    公开(公告)号：US07434114B2

    公开(公告)日：2008-10-07

    申请号：US11326622

    申请日：2006-01-07

    申请人： Soon-Bok Jang ,  Young-Gyu Kang

    发明人： Soon-Bok Jang ,  Young-Gyu Kang

    IPC分类号： G06K5/04

    CPC分类号： G06F13/423

    摘要： A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

    摘要翻译： 一种补偿PCI Express总线的字节偏移的方法，所述方法包括确定接收到的数据是否处于训练序列中，基于包括在训练序列中的逗号符号来设置与每个通道相对应的对准点，当 所接收的数据处于训练序列中，并且当接收到的数据不在训练序列中时，通过反映在接收到的数据上的跳过符号的相加或移除通过四个通道中的每一个来移动对准点。 因此，即使添加或删除跳过符号，也可以有效地补偿PCI Express总线的字节偏移。

    Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same
    8.
    发明申请
    Method of compensating for a byte skew of PCI express and PCI express physical layer receiver for the same 有权
    补偿PCI Express和PCI Express物理层接收机的字节偏移的方法

    公开(公告)号：US20060156083A1

    公开(公告)日：2006-07-13

    申请号：US11326622

    申请日：2006-01-07

    申请人： Soon-Bok Jang ,  Young-Gyu Kang

    发明人： Soon-Bok Jang ,  Young-Gyu Kang

    IPC分类号： G11B20/20 ,  G06K5/04 ,  G11B5/00

    CPC分类号： G06F13/423

    摘要： A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received data are in the training sequence, and shifting the alignment point by reflecting an addition or a removal of a skip symbol on the received data through each of the four lanes when the received data are not in the training sequence. Therefore, the byte skew of the PCI Express bus may be effectively compensated for despite the addition or the removal of the skip symbol.

    摘要翻译： 一种补偿PCI Express总线的字节偏移的方法，所述方法包括确定接收到的数据是否处于训练序列中，基于包括在训练序列中的逗号符号来设置与每个通道相对应的对准点，当 所接收的数据处于训练序列中，并且当接收到的数据不在训练序列中时，通过反映在接收到的数据上的跳过符号的相加或移除通过四个通道中的每一个来移动对准点。 因此，即使添加或删除跳过符号，也可以有效地补偿PCI Express总线的字节偏移。