公开(公告)号：USD452114S1

公开(公告)日：2001-12-18

申请号：US29137277

申请日：2001-02-15

Applicant: Yu Chen Lin

Designer： Yu Chen Lin

公开(公告)号：US06226185B1

公开(公告)日：2001-05-01

申请号：US09449823

申请日：1999-11-26

Applicant: Yu Chen Lin

Inventor： Yu Chen Lin

IPC: H05K720

CPC classification number: H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat sink assembly includes a socket secured on a printed circuit board, an integrated circuit secured on the socket, a heat sink disposed on the integrated circuit, and a resilient retainer clip biasing the heat sink to engage with the socket. An anti-electromagnetic wave device includes a leg engaged with the printed circuit board and a head engaged through a lug of the socket and engaged with one arm of the resilient retainer clip for dissipating the electromagnetic wave that may be transmitted to the integrated circuit.

Abstract translation: 散热器组件包括固定在印刷电路板上的插座，固定在插座上的集成电路，设置在集成电路上的散热器以及偏置散热器与插座接合的弹性保持夹。 抗电磁波装置包括与印刷电路板接合的脚和通过插座的凸耳接合并与弹性保持夹的一个臂接合的头部，用于耗散可传输到集成电路的电磁波。

公开(公告)号：US5892261A

公开(公告)日：1999-04-06

申请号：US780670

申请日：1997-01-07

Applicant: Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

Inventor： Shi-Tron Lin ,  Ta-Lee Yu ,  Chau Neng Wu ,  Yu Chen Lin ,  Yang Sen Yeh

IPC: H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

Abstract: An apparatus and method for use in a semiconductor memory device to reduce internal circuit damage resulting from the effects of electro-static discharge (ESD) on a bitline pull-up or other type of circuit. Each of a plurality of bitlines in the memory device are coupled to a source terminal of a corresponding N-type MOSFET. Each source terminal is formed in a separate corner portion of at least one active region of the memory device, and is coupled to a given bitline via a bitline contact arranged in the corner portion. Each drain terminal of the N-type MOSFETS is formed from another portion of the active region and is coupled to a VDD supply of the memory device via a VDD contact. A gate terminal of a given MOSFET is formed from a polysilicon gate region overlying a channel in the active region. The gate region has an approximately 90.degree. bend therein such that a bitline contact in the corresponding corner portion of the active region is located between the bend and an outer peripheral edge of the corner portion. This layout allows the contact-to-diffusion-edge and contact-to-gate-edge spacings of the VDD contacts to be increased such that internal circuit ESD immunity of the memory device is improved without impacting device dimension and layout area constraints.

Abstract translation: 一种在半导体存储器件中使用的装置和方法，用于减少由于位线上拉电路或其它类型电路上的静电放电（ESD）的影响而产生的内部电路损坏。 存储器件中的多个位线中的每一个与相应的N型MOSFET的源极耦合。 每个源极端子形成在存储器件的至少一个有源区域的单独拐角部分中，并且经由布置在拐角部分中的位线接触件耦合到给定的位线。 N型MOSFET的每个漏极端子由有源区域的另一部分形成，并通过VDD触点耦合到存储器件的VDD电源。 给定MOSFET的栅极端子由覆盖有源区域中的沟道的多晶硅栅极区域形成。 栅极区域在其中具有大约90度的弯曲，使得有源区域的相应拐角部分中的位线接触位于弯曲部分和拐角部分的外周边缘之间。 该布局允许增加VDD触点的接触到扩散边缘和接触到栅极边缘间隔，使得存储器件的内部电路ESD抗扰度得到改善，而不会影响器件尺寸和布局面积限制。