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1.
公开(公告)号:US07713855B2
公开(公告)日:2010-05-11
申请号:US11780484
申请日:2007-07-20
申请人: Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
发明人: Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
IPC分类号: H01L21/3205 , H01L21/4763
CPC分类号: H01L21/76897 , H01L21/76834 , H01L21/76885 , H01L21/76895 , H01L27/10888
摘要: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
摘要翻译: 一种用于形成位线接触插塞的方法包括:提供包括晶体管的衬底,所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层,位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺,以蚀刻位线接触材料层和硬掩模层,并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极,覆盖栅极结构的一部分并连接到源极/漏极的导电层,以及布置在导电层上的位线接触插塞, 直接连接到导电层。
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2.
公开(公告)号:US20080268640A1
公开(公告)日:2008-10-30
申请号:US11780484
申请日:2007-07-20
申请人: Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
发明人: Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
IPC分类号: H01L21/441 , H01L29/78
CPC分类号: H01L21/76897 , H01L21/76834 , H01L21/76885 , H01L21/76895 , H01L27/10888
摘要: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
摘要翻译: 一种用于形成位线接触插塞的方法包括:提供包括晶体管的衬底,所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层,位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺,以蚀刻位线接触材料层和硬掩模层,并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极,覆盖栅极结构的一部分并连接到源极/漏极的导电层,以及布置在导电层上的位线接触插塞, 直接连接到导电层。
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公开(公告)号:US20050269293A1
公开(公告)日:2005-12-08
申请号:US11141978
申请日:2005-05-31
申请人: Chen-Lung Fan , Kai-Chih Chang , Jih-Jse Lin , Jing-Kae Liou , Ta-Chin Chen , Srisuda Thitinun , Sok-Kiow Tan
发明人: Chen-Lung Fan , Kai-Chih Chang , Jih-Jse Lin , Jing-Kae Liou , Ta-Chin Chen , Srisuda Thitinun , Sok-Kiow Tan
CPC分类号: H01L21/32136 , C23F4/00
摘要: Disclosed is a seasoning method for an etch chamber for improving the passing rate, comprising the steps of: introducing a wafer or plural control wafers into the etch chamber; introducing reacting gases into the etch chamber; applying power to top and bottom electrodes of the etch chamber to plasmarize the reacting gases; and adjusting the gate valve of the etch chamber to 90 to 100% of the fully open position, thereby reducing the amount of by-products and eliminating the factors for reducing the passing rate. The seasoning method of this invention is based on a low pressure, high flow-rate sluicing mechanism, where the atmospheric flow and high vacuuming ability would remove the maximum amount of polymer particles and flaking from the etch chamber.
摘要翻译: 公开了一种用于提高通过率的蚀刻室的调味方法,包括以下步骤:将晶片或多个控制晶片引入蚀刻室; 将反应气体引入蚀刻室; 将电力施加到蚀刻室的顶部和底部电极以使反应气体均质化; 并且将蚀刻室的闸阀调整到完全打开位置的90至100%,从而减少副产物的量并消除降低通过率的因素。 本发明的调味方法是基于低压,高流速的洗涤机构,其中大气流量和高吸尘能力将去除最大量的聚合物颗粒和从蚀刻室剥落。
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