Seasoning method for etch chamber
    1.
    发明申请
    Seasoning method for etch chamber 审中-公开
    蚀刻室调味方法

    公开(公告)号:US20050269293A1

    公开(公告)日:2005-12-08

    申请号:US11141978

    申请日:2005-05-31

    IPC分类号: B44C1/22 C23F1/00 C23F4/00

    CPC分类号: H01L21/32136 C23F4/00

    摘要: Disclosed is a seasoning method for an etch chamber for improving the passing rate, comprising the steps of: introducing a wafer or plural control wafers into the etch chamber; introducing reacting gases into the etch chamber; applying power to top and bottom electrodes of the etch chamber to plasmarize the reacting gases; and adjusting the gate valve of the etch chamber to 90 to 100% of the fully open position, thereby reducing the amount of by-products and eliminating the factors for reducing the passing rate. The seasoning method of this invention is based on a low pressure, high flow-rate sluicing mechanism, where the atmospheric flow and high vacuuming ability would remove the maximum amount of polymer particles and flaking from the etch chamber.

    摘要翻译: 公开了一种用于提高通过率的蚀刻室的调味方法,包括以下步骤:将晶片或多个控制晶片引入蚀刻室; 将反应气体引入蚀刻室; 将电力施加到蚀刻室的顶部和底部电极以使反应气体均质化; 并且将蚀刻室的闸阀调整到完全打开位置的90至1​​00%,从而减少副产物的量并消除降低通过率的因素。 本发明的调味方法是基于低压,高流速的洗涤机构,其中大气流量和高吸尘能力将去除最大量的聚合物颗粒和从蚀刻室剥落。

    Multi-zone temperature control for semiconductor wafer
    2.
    发明授权
    Multi-zone temperature control for semiconductor wafer 有权
    半导体晶圆的多区域温度控制

    公开(公告)号:US08404572B2

    公开(公告)日:2013-03-26

    申请号:US12370746

    申请日:2009-02-13

    IPC分类号: H01L21/425

    摘要: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

    摘要翻译: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源,每个冷却剂源流体耦合到相应的一个流体导管,并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

    MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER
    3.
    发明申请
    MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER 有权
    用于半导体波形的多区温度控制

    公开(公告)号:US20100210041A1

    公开(公告)日:2010-08-19

    申请号:US12370746

    申请日:2009-02-13

    摘要: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

    摘要翻译: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源,每个冷却剂源流体耦合到相应的一个流体管道,并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

    Sealing layer of a field effect transistor
    4.
    发明授权
    Sealing layer of a field effect transistor 有权
    场效应晶体管的密封层

    公开(公告)号:US08258588B2

    公开(公告)日:2012-09-04

    申请号:US12757241

    申请日:2010-04-09

    CPC分类号: H01L29/4983 H01L29/6656

    摘要: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

    摘要翻译: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体,在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层,其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度,由此所述场效应晶体管 在基板表面几乎没有凹陷。