公开(公告)号：US20100213649A1

公开(公告)日：2010-08-26

申请号：US12472750

申请日：2009-05-27

申请人： Hong Wen Lee ,  Yi Ming Chang

发明人： Hong Wen Lee ,  Yi Ming Chang

IPC分类号： F16F3/04 ,  H05K13/00

CPC分类号： F16F15/06 ,  G06F1/183 ,  H05K1/0215 ,  H05K2201/0311 ,  H05K2201/09072 ,  H05K2201/1031 ,  Y02P70/611 ,  Y10T29/49002

摘要： A shock absorber and an assembling method of an electronic device using the same are provided. The shock absorber includes a first connecting portion, a second connecting portion and a number of elastic arms. The two connecting portions respectively connect to a housing and a circuit board of the electronic device. Two ends of each elastic arm are respectively connected to the two connecting portions to buffer the relative movement between the housing and the circuit board. The method includes the following steps. First, the shock absorber including the first connecting portion, the second connecting portion and the elastic arms is provided. Then the second connecting portion is connected to a surface of the circuit board surrounding a through hole of the circuit board. After connecting the second connecting portion, the housing is connected to the first connecting portion.

摘要翻译： 提供了一种使用其的电子设备的减震器和组装方法。 减震器包括第一连接部分，第二连接部分和多个弹性臂。 两个连接部分分别连接到电子设备的壳体和电路板。 每个弹性臂的两端分别连接到两个连接部分，以缓冲壳体和电路板之间的相对移动。 该方法包括以下步骤。 首先，提供包括第一连接部分，第二连接部分和弹性臂的减震器。 然后，第二连接部分连接到电路板的围绕电路板的通孔的表面。 在连接第二连接部分之后，壳体连接到第一连接部分。

公开(公告)号：US07713855B2

公开(公告)日：2010-05-11

申请号：US11780484

申请日：2007-07-20

申请人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

发明人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10888

摘要： A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

摘要翻译： 一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞， 直接连接到导电层。

公开(公告)号：US20230023998A1

公开(公告)日：2023-01-26

申请号：US17853861

申请日：2022-06-29

申请人： Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

发明人： Chun-Cheng Lin ,  Shy-Luen Chern ,  Chih-Hsiang Tang ,  Hong-Wen Lee

IPC分类号： H01R13/17 ,  H01R13/629 ,  H01R13/502 ,  H01R13/24

摘要： An electrical connector assembly including a first connector and a second connector to be mated with each other is provided. The first connector includes a first body, and at least one first terminal and multiple second terminals disposed therein. The second terminals are symmetrically arranged at opposite sides of the first terminal. The second connector includes a second body, at least one third terminal movably disposed in the second body, multiple fourth terminals disposed in the second body and symmetrically arranged at opposite sides of the third terminal, and a driving module electrically connected to at least one of the fourth terminals and structurally connected to the third terminal. In the mating process of the first and second connector, the second terminals and the fourth terminals are electrically connected firstly, to trigger the driving module to move the third terminal to be structurally and electrically connected to the first terminal.

公开(公告)号：US20080268640A1

公开(公告)日：2008-10-30

申请号：US11780484

申请日：2007-07-20

申请人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

发明人： Yu-Chung Fang ,  Hong-Wen Lee ,  Kuo-Chung Chen ,  Jen-Jui Huang ,  Jing-Kae Liou

IPC分类号： H01L21/441 ,  H01L29/78

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10888

摘要： A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

摘要翻译： 一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。 晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞， 直接连接到导电层。

公开(公告)号：US20080303103A1

公开(公告)日：2008-12-11

申请号：US11932620

申请日：2007-10-31

申请人： Kuo Chung CHEN ,  Jen-Jui HUANG ,  Hong Wen LEE

发明人： Kuo Chung CHEN ,  Jen-Jui HUANG ,  Hong Wen LEE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/66613

摘要： The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such that a partial surface of the substrate becomes a curve surface, forming a sacrificial layer on the curve surface, forming a first doped region in the substrate and under the hard mask layer, forming a gate stack within the opening, removing the hard mask layer, forming a spacer on a sidewall of the gate stack, and forming a second doped region in the substrate and under the spacer. The second doped region has a dopant concentration is larger than that of the first doped region. Therefore, the oxide layer increases the surface area of the substrate so as to increase the channel length. Thus, the leakage between the source region and the drain region can be improved.

摘要翻译： 本发明提供一种半导体结构及其形成方法。 该方法包括以下步骤：提供衬底，在衬底上形成具有开口的掩模层，局部氧化衬底以在开口内形成氧化物层，去除氧化物层，使得衬底的部分表面变为曲线 在所述曲面上形成牺牲层，在所述衬底中并在所述硬掩模层之下形成第一掺杂区域，在所述开口内形成栅叠层，去除所述硬掩膜层，在所述栅叠层的侧壁上形成间隔物 并且在所述衬底中并在所述间隔物之下形成第二掺杂区域。 第二掺杂区域的掺杂浓度大于第一掺杂区域的掺杂浓度。 因此，氧化物层增加了衬底的表面积，从而增加了沟道长度。 因此，可以提高源极区域和漏极区域之间的泄漏。

公开(公告)号：US07170740B1

公开(公告)日：2007-01-30

申请号：US11307005

申请日：2006-01-19

申请人： Jen-Hao Liu ,  San-Yang Lo ,  Hong-Wen Lee

发明人： Jen-Hao Liu ,  San-Yang Lo ,  Hong-Wen Lee

IPC分类号： H05K7/20

CPC分类号： G06F1/1662 ,  G06F1/1616 ,  G06F1/1656

摘要： A foldable support structure suitable for a notebook is provided. The notebook includes a keyboard, a circuit board, and a support frame, disposed above the circuit board for carrying the edge of the keyboard. The support structure is disposed inside an opening of the support frame for supporting the bottom of the keyboard. The support structure and the support frame are fabricated as a whole. The support structure includes a flexibility section, a support section and a pedestal section. The flexibility section is connected to the support frame and the support section. The pedestal section is connected to the support section. The deformed flexibility section keeps the support section away from the circuit board. The support section has a support surface for supporting the keyboard. The pedestal section is suitable for connecting the circuit board such that a distance is kept between the support section and the circuit board.

摘要翻译： 提供了一种适用于笔记本的可折叠支撑结构。 笔记本电脑包括一个键盘，一个电路板和一个支撑框架，它设置在电路板的上方，用于承载键盘的边缘。 支撑结构设置在支撑框架的开口内，用于支撑键盘的底部。 支撑结构和支撑框架整体制造。 支撑结构包括柔性部分，支撑部分和基座部分。 柔性部分连接到支撑框架和支撑部分。 基座部分连接到支撑部分。 变形的柔性部分使支撑部分远离电路板。 支撑部分具有用于支撑键盘的支撑表面。 基座部分适于连接电路板，使得支撑部分和电路板之间保持一定距离。

公开(公告)号：US20090061588A1

公开(公告)日：2009-03-05

申请号：US11969924

申请日：2008-01-07

申请人： Chang-Ho Yeh ,  Hong-Wen Lee

发明人： Chang-Ho Yeh ,  Hong-Wen Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876

摘要： A method for fabricating a dynamic random access memory is provided. A substrate having two trench capacitors therein is provided, an isolation structure protruding from a surface of the substrate is formed on each trench capacitor, a spacer is formed on the substrate at two sides of each of the isolation structures, and a block layer is formed between each spacer and each isolation structure and between each spacer and the substrate. A trench is formed in the substrate between the trench capacitors, and partial of the trench is located under partial of the spacers and partial of the block layer. The spacers, the block layer, and partial of the isolation structures above the trench are removed. A gate structure protruding from the surface of the substrate is formed in the trench. A doped region is formed in the substrate at each of two sides of the gate structure.

摘要翻译： 提供了一种用于制造动态随机存取存储器的方法。 提供一种其中具有两个沟槽电容器的衬底，在每个沟槽电容器上形成从衬底表面突出的隔离结构，在每个隔离结构的两侧在衬底上形成间隔物，形成阻挡层 在每个间隔物和每个隔离结构之间以及每个间隔物和基底之间。 在沟槽电容器之间的衬底中形成沟槽，并且沟槽的部分位于衬垫的部分部分和阻挡层的部分之下。 去除间隔物，阻挡层和沟槽上方的隔离结构的部分。 在沟槽中形成从衬底表面突出的栅极结构。 在栅极结构的两侧的每一侧的基板中形成掺杂区域。