公开(公告)号：US20230225039A1

公开(公告)日：2023-07-13

申请号：US18118039

申请日：2023-03-06

申请人： Yu-Huan CHEN ,  Yu-Chih HUANG ,  Ming-Hsun TSAI ,  Shang-Chieh CHIEN ,  Heng-Hsin LIU

发明人： Yu-Huan CHEN ,  Yu-Chih HUANG ,  Ming-Hsun TSAI ,  Shang-Chieh CHIEN ,  Heng-Hsin LIU

IPC分类号： H05G2/00

CPC分类号： H05G2/006 ,  H05G2/008

摘要： A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. In some embodiments, a nozzle tube is arranged within the nozzle of the droplet generator, and the nozzle tube includes a structured nozzle pattern configured to provide an angular momentum to the target droplets.

公开(公告)号：US20130009144A1

公开(公告)日：2013-01-10

申请号：US13286902

申请日：2011-11-01

申请人： Huang-Chung CHENG ,  Yu-Chih HUANG ,  Po-Yu YANG ,  Shin-Chuan CHIANG ,  Huai-An LI

发明人： Huang-Chung CHENG ,  Yu-Chih HUANG ,  Po-Yu YANG ,  Shin-Chuan CHIANG ,  Huai-An LI

IPC分类号： H01L29/24

CPC分类号： H01L29/78603 ,  H01L27/1225 ,  H01L29/78606 ,  H01L29/7869

摘要： A top-gate transistor array substrate includes a transparent substrate with a plane, an ion release layer, a pixel array, and a first insulating layer. The ion release layer is disposed on the transparent substrate and completely covers the plane. The pixel array is disposed on the ion release layer and includes a plurality of transistors and a plurality of pixel electrodes. Each of the transistors includes a source, a drain, a gate and a MOS (metal oxide semiconductor) layer. The drain, the source and the MOS layer are disposed on the ion release layer. The pixel electrodes are electrically connected to the drains respectively. The gate is disposed above the MOS layer. The first insulating layer is disposed between the MOS layers and the gates. The MOS layer contacts the ion release layer. The ion release layer can release a plurality of ions into the MOS layers.

摘要翻译： 顶栅晶体管阵列基板包括具有平面的透明基板，离子剥离层，像素阵列和第一绝缘层。 离子剥离层设置在透明基板上并完全覆盖平面。 像素阵列设置在离子剥离层上，并且包括多个晶体管和多个像素电极。 每个晶体管包括源极，漏极，栅极和MOS（金属氧化物半导体）层。 漏极，源极和MOS层设置在离子剥离层上。 像素电极分别与漏极电连接。 栅极设置在MOS层的上方。 第一绝缘层设置在MOS层和栅极之间。 MOS层与离子释放层接触。 离子剥离层可以将多个离子释放到MOS层中。