公开(公告)号：US07176135B2

公开(公告)日：2007-02-13

申请号：US10753826

申请日：2004-01-08

申请人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

发明人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01I21/302 ,  H01I21/461

CPC分类号： H01L21/31053

摘要： In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

摘要翻译： 根据本发明的目的，提供了一种新的方法来调节边缘珠移除隆起并进一步防止尖端或尖端形状的边缘去除边缘，从而防止化学机械过程之后的低k电介质膜的剥离 抛光低k电影。

公开(公告)号：US20050151227A1

公开(公告)日：2005-07-14

申请号：US10753826

申请日：2004-01-08

申请人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

发明人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L23/544

CPC分类号： H01L21/31053

摘要： In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

摘要翻译： 根据本发明的目的，提供了一种新的方法来调节边缘珠移除隆起并进一步防止尖端或尖端形状的边缘去除边缘，从而防止化学机械过程之后的低k电介质膜的剥离 抛光低k电影。

公开(公告)号：US06706637B2

公开(公告)日：2004-03-16

申请号：US10143700

申请日：2002-05-09

申请人： Yu-Huei Chen ,  Yao-Yi Cheng ,  Sung-Ming Jang ,  Chen-Hua Yu

发明人： Yu-Huei Chen ,  Yao-Yi Cheng ,  Sung-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21311

CPC分类号： H01L21/76826 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76822

摘要： Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

摘要翻译： 在用于形成双镶嵌孔的方法中，表面处理了第一介电层，以形成具有不同于第一块体组合物的第一表面组成的经表面处理的第一介电层。 然后在表面处理的第一电介质层上形成具有第二体积组成的第二电介质层。 最后，然后通过第二电介质层形成与通过经表面处理的第一介电层形成的通孔相邻并与其重叠的沟槽。 在本发明中，当通过第二电介质层形成沟槽时，通过检测第二散装组合物和第一表面组合物之间的差异来确定端点。

公开(公告)号：US06599838B1

公开(公告)日：2003-07-29

申请号：US10188442

申请日：2002-07-02

申请人： Tsu Shih ,  Sung-Ming Jang

发明人： Tsu Shih ,  Sung-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/7684

摘要： A method for forming a metal filled semiconductor feature including a low dielectric constant CMP polishing stop layer for improving a CMP polishing process including providing a semiconductor processing surface having a anisotropically etched semiconductor feature formed through a thickness including a second dielectric insulating layer overlying a first dielectric insulating layer, the second dielectric insulating layer having a CMP material removal rate in a CMP process less than about ½ of a CMP material removal rate of the first dielectric insulating layer in the CMP process; filling the anisotropically etched semiconductor feature with a metal to form a metal filled semiconductor feature; and, planarizing according to the CMP process excess material including the metal overlying the second dielectric insulating layer.

摘要翻译： 一种形成金属填充半导体器件的方法，包括用于改善CMP抛光工艺的低介电常数CMP抛光停止层，包括提供具有各向异性蚀刻半导体特征的半导体处理表面，所述半导体处理表面通过厚度形成，所​​述厚度包括覆盖在第一电介质 绝缘层，所述第二介电绝缘层在CMP工艺中具有小于CMP工艺中第一介电绝缘层的CMP材料去除速率的约1/2的CMP材料去除速率; 用金属填充各向异性蚀刻的半导体特征以形成金属填充的半导体特征; 并且根据CMP工艺平面化包括覆盖在第二介电绝缘层上的金属的多余材料。

公开(公告)号：US06589852B1

公开(公告)日：2003-07-08

申请号：US10154463

申请日：2002-05-23

申请人： Tsu Shih ,  Sung-Ming Jang

发明人： Tsu Shih ,  Sung-Ming Jang

IPC分类号： H01L2176

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for avoiding a step height over an alignment mark area including providing at least one alignment mark area disposed at a semiconductor wafer process surface periphery said alignment mark area having alignment marks anisotropically etched into the semiconductor wafer process surface; depositing a first insulating dielectric layer over an active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; planarizing the first insulating dielectric layer; depositing a polysilicon layer over the active area of the semiconductor wafer process surface to include covering the at least one alignment mark area; and, anisotropically etching the polysilicon layer through a thickness over the at least one alignment mark area to form an opening extending no further than about the first insulating dielectric layer to minimize a step height.

摘要翻译： 一种用于避免对准标记区域上的台阶高度的方法，包括提供设置在半导体晶片工艺表面周围的至少一个对准标记区域，所述对准标记区域具有各向异性蚀刻到半导体晶片工艺表面中的对准标记; 在所述半导体晶片工艺表面的有效区域上沉积第一绝缘介电层以包括覆盖所述至少一个对准标记区域; 平面化第一绝缘介电层; 在所述半导体晶片工艺表面的有源区上沉积多晶硅层以包括覆盖所述至少一个对准标记区域; 并且通过所述至少一个对准标记区域上的厚度各向异性地蚀刻所述多晶硅层，以形成不超过所述第一绝缘介电层延伸的开口，以使台阶高度最小化。