公开(公告)号：US08839081B2

公开(公告)日：2014-09-16

申请号：US13609034

申请日：2012-09-10

申请人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

发明人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

IPC分类号： H03M13/00 ,  H04L1/00

CPC分类号： H04L1/0068

摘要： Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

摘要翻译： 提供了用于数字信号处理器上的速率匹配和去速率匹配的设备，系统和方法。 在一个实施例中，用于速率匹配和去速率匹配的设备包括用于接收多个数据块的接口和被配置为预先计算多个块共同的置换参数的数字信号处理器，其中多个块是 受制于一组给定的打孔参数并接收一组预先计算的穿刺阈值。 对于多个块中的一个或多个块，DSP从预先计算的穿孔阈值计算块签名; 将块签名与一组预先计算的区域签名中的一个匹配，导出与一个预先计算的区域签名相对应的区域索引，并将对应于区域索引的预先计算的置换和删截变换应用于该块。

公开(公告)号：US20130007382A1

公开(公告)日：2013-01-03

申请号：US13609034

申请日：2012-09-10

申请人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

发明人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

IPC分类号： G06F12/00

CPC分类号： H04L1/0068

摘要： Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

摘要翻译： 提供了用于数字信号处理器上的速率匹配和去速率匹配的设备，系统和方法。 在一个实施例中，用于速率匹配和去速率匹配的设备包括用于接收多个数据块的接口和被配置为预先计算多个块共同的置换参数的数字信号处理器，其中多个块是 受制于一组给定的打孔参数并接收一组预先计算的穿刺阈值。 对于多个块中的一个或多个块，DSP从预先计算的穿孔阈值计算块签名; 将块签名与一组预先计算的区域签名中的一个匹配，导出与一个预先计算的区域签名相对应的区域索引，并将对应于区域索引的预先计算的置换和删截变换应用于该块。

公开(公告)号：US08806310B2

公开(公告)日：2014-08-12

申请号：US13100190

申请日：2011-05-03

申请人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

发明人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

IPC分类号： H03M13/03 ,  H04L1/00

CPC分类号： H04L1/0068

摘要： Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

摘要翻译： 提供了用于数字信号处理器上的速率匹配和去速率匹配的系统和方法。 例如，存在用于速率匹配和去速率匹配的系统，其中系统包括被配置为包含多个数据块的存储器，以及数字信号处理器，被配置为预先计算多个块共同的置换参数 ，其中所述多个块经受一组给定的删截参数。 数字信号处理器被配置为通过从预先计算的穿孔阈值计算块签名来处理多个块中的每个块，将块签名与一组预先计算的区域签名中的一个相匹配，导出对应于 一个匹配的预先计算的区域签名，并且将对应于区域索引的预先计算的置换和删截变换应用于块。

公开(公告)号：US20110276767A1

公开(公告)日：2011-11-10

申请号：US13100190

申请日：2011-05-03

申请人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

发明人： Yuan Li ,  Julien Nicolas ,  Jianbin Zhu

IPC分类号： G06F12/00

CPC分类号： H04L1/0068

摘要： Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

摘要翻译： 提供了用于数字信号处理器上的速率匹配和去速率匹配的系统和方法。 例如，存在用于速率匹配和去速率匹配的系统，其中系统包括被配置为包含多个数据块的存储器，以及数字信号处理器，被配置为预先计算多个块共同的置换参数 ，其中所述多个块经受一组给定的删截参数。 数字信号处理器被配置为通过从预先计算的穿孔阈值计算块签名来处理多个块中的每个块，将块签名与一组预先计算的区域签名中的一个相匹配，导出对应于 一个匹配的预先计算的区域签名，并且将对应于区域索引的预先计算的置换和删截变换应用于块。

公开(公告)号：US20180267930A1

公开(公告)日：2018-09-20

申请号：US15919709

申请日：2018-03-13

申请人： Jianbin Zhu ,  Yuan Li

发明人： Jianbin Zhu ,  Yuan Li

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F9/38

摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.

公开(公告)号：US20130007555A1

公开(公告)日：2013-01-03

申请号：US13608905

申请日：2012-09-10

申请人： Jianbin Zhu ,  Yuan Li ,  Tao Zhang

发明人： Jianbin Zhu ,  Yuan Li ,  Tao Zhang

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H04L1/005 ,  H03M13/1515 ,  H03M13/29 ,  H03M13/2957 ,  H04L1/006

摘要： Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

摘要翻译： 提供了用于尾端终止的方法和装置，其包括解码器，该解码器包括被配置为向前状态度量和后向状态量度的处理器，其中，从存储器取出后向状态量度的初始状态的每次迭代，并且在没有 来自解码迭代的反馈。 每个解码迭代基本相同，并且预先计算的向后状态度量用于后续迭代。 解码器可以包括turbo解码器或radix-4解码器。

公开(公告)号：US20180267932A1

公开(公告)日：2018-09-20

申请号：US15919752

申请日：2018-03-13

申请人： Jianbin Zhu ,  Yuan Li

发明人： Jianbin Zhu ,  Yuan Li

IPC分类号： G06F15/80 ,  G06F9/30

摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.

公开(公告)号：US20180267931A1

公开(公告)日：2018-09-20

申请号：US15919727

申请日：2018-03-13

申请人： Yuan Li ,  Jianbin Zhu

发明人： Yuan Li ,  Jianbin Zhu

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F12/0815

摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each PE may have a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.

公开(公告)号：US20180267809A1

公开(公告)日：2018-09-20

申请号：US15919774

申请日：2018-03-13

申请人： Yuan Li ,  Jianbin Zhu

发明人： Yuan Li ,  Jianbin Zhu

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34 ,  G06F13/16

CPC分类号： G06F15/8023 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3808 ,  G06F9/3867 ,  G06F9/3885 ,  G06F12/0815 ,  G06F13/1673 ,  G06F2212/1021 ,  Y02D10/14

摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise an arithmetic logic unit (ALU), a data buffer associated with the ALU, and an indicator associated with the data buffer to indicate whether a piece of data inside the data buffer is to be reused for repeated execution of a same instruction as a pipeline stage.

公开(公告)号：US08930791B2

公开(公告)日：2015-01-06

申请号：US13608720

申请日：2012-09-10

申请人： Yuan Li ,  Jianbin Zhu ,  Tao Zhang

发明人： Yuan Li ,  Jianbin Zhu ,  Tao Zhang

IPC分类号： H03M13/00 ,  H04L1/00

CPC分类号： H04L1/005 ,  H04L1/006

摘要： In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.

摘要翻译： 在一个实施例中，用于在turbo解码中早期停止的设备包括：处理器，被配置为接收待解码的数据块，比较由解码迭代得到的硬判决位，并将解码比特的对数似然比（LLR）的最小值与 阈。 处理器配置为将硬判决与先前的迭代结果进行匹配。 处理器可以被配置为在与先前的迭代结果匹配的硬判决匹配之后设置早期停止规则。 处理器可以被配置为当输出比特的最小可靠性超过阈值时设置早期停止规则。