公开(公告)号：US08593854B1

公开(公告)日：2013-11-26

申请号：US13476366

申请日：2012-05-21

申请人： Yue-Der Chih ,  Luan Conn Tran

发明人： Yue-Der Chih ,  Luan Conn Tran

IPC分类号： G11C11/00

CPC分类号： H01L45/04 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0083 ,  G11C2013/0088 ,  G11C2213/79 ,  G11C2213/82

摘要： An array and forming method for resistive-RAM (RRAM) devices provides for the simultaneous selection of multiple bit cells and the simultaneous forming of the RRAM resistive elements within the selected bit cells. The bit cells each include a resistive element and a transistor and are arranged vertically along vertical bit lines. The resistive elements of the bit cells are coupled to source lines that are parallel to word lines and perpendicular to the vertical bit lines. The bit lines are maintained at different biases. A high voltage is applied to one of the source lines coupled to adjacent resistive elements of bit cells disposed along more than one vertical bit line. When the associated transistors are turned on by a sufficiently high gate voltage, the desired RRAM resistive elements along one of the bit lines are formed without stressing other bit cells of the array.

摘要翻译： 用于电阻RAM（RRAM）器件的阵列和形成方法提供了同时选择多个位单元并且在所选位单元内同时形成RRAM电阻元件。 每个位单元都包括电阻元件和晶体管，并且沿着垂直位线垂直布置。 位单元的电阻元件耦合到与字线平行并垂直于垂直位线的源极线。 位线保持不同的偏置。 高电压施加到耦合到沿着多于一个垂直位线布置的位单元的相邻电阻元件的源极线之一。 当相关联的晶体管导通足够高的栅极电压时，沿着位线之一的期望的RRAM电阻元件形成，而不会压迫阵列的其它位单元。