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公开(公告)号:US20190051353A1
公开(公告)日:2019-02-14
申请号:US16161285
申请日:2018-10-16
发明人: Eun-chu OH , Pil-sang Yoon , Jun-jin Kong , Hong-rak Son
CPC分类号: G11C13/0069 , G06F11/1048 , G06F12/00 , G06F12/0238 , G06F2212/7201 , G06F2212/7202 , G11C8/06 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C2013/0088 , G11C2213/71 , G11C2213/72 , H03M13/05 , H03M13/27
摘要: A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.
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公开(公告)号:US20180330782A1
公开(公告)日:2018-11-15
申请号:US16043688
申请日:2018-07-24
发明人: Deepak Chandra SEKAR , Wayne Frederick ELLIS , Brent Steven HAUKNESS , Gary Bela BRONNER , Thomas VOGELSANG
CPC分类号: G11C13/0028 , G11C7/08 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0083 , G11C2013/0088 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.
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公开(公告)号:US10068642B1
公开(公告)日:2018-09-04
申请号:US15696118
申请日:2017-09-05
发明人: Kunifumi Suzuki , Kazuhiko Yamamoto
CPC分类号: G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092 , G11C2213/77 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/148 , H01L45/1616
摘要: A memory device includes a control circuit configured to (i) start a first application of a first voltage between a first conductive layer and a third conductive layer, (ii) start a second application of the first voltage between a second conductive layer and the third conductive layer after a lapse of a first delay time since the start of the first application of the first voltage, and (iii) start an application of a second voltage, which is smaller than the first voltage, between the first conductive layer and the third conductive layer after a lapse of a second delay time since the start of the second application of the first voltage between the second conductive layer and the third conductive layer.
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公开(公告)号:US20180190349A1
公开(公告)日:2018-07-05
申请号:US15858801
申请日:2017-12-29
发明人: Hernan A. Castro
CPC分类号: G11C13/003 , G06F3/061 , G06F3/0658 , G06F3/0673 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/15 , G11C2213/71 , G11C2213/77
摘要: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
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公开(公告)号:US09990995B2
公开(公告)日:2018-06-05
申请号:US15854934
申请日:2017-12-27
发明人: Andrea Redaelli
CPC分类号: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
摘要: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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公开(公告)号:US20180122474A1
公开(公告)日:2018-05-03
申请号:US15854934
申请日:2017-12-27
发明人: Andrea Redaelli
CPC分类号: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
摘要: Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to a selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data.
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公开(公告)号:US09899082B2
公开(公告)日:2018-02-20
申请号:US15261810
申请日:2016-09-09
发明人: Akira Katayama
IPC分类号: G11C13/00
CPC分类号: G11C13/0069 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2013/0085 , G11C2013/0088 , G11C2213/79
摘要: According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.
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公开(公告)号:US09881673B2
公开(公告)日:2018-01-30
申请号:US15488828
申请日:2017-04-17
发明人: Andrea Redaelli
CPC分类号: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
摘要: Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of resistive storage elements in a one-to-one relationship and sense circuitry coupled to the plurality of select devices.
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公开(公告)号:US09773549B2
公开(公告)日:2017-09-26
申请号:US15401419
申请日:2017-01-09
发明人: Theodoros A. Antonakopoulos , Evangelos Eleftheriou , Ioannis Koltsidas , Peter Mueller , Aspasia Palli , Roman A. Pletka
IPC分类号: G11C13/00
CPC分类号: G11C13/004 , G11C7/10 , G11C7/106 , G11C7/1087 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C14/0045 , G11C2013/0088
摘要: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.
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公开(公告)号:US20170256313A1
公开(公告)日:2017-09-07
申请号:US15261810
申请日:2016-09-09
发明人: Akira KATAYAMA
IPC分类号: G11C13/00
CPC分类号: G11C13/0069 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C2013/0085 , G11C2013/0088 , G11C2213/79
摘要: According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.
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