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    Method of processing digital audio signals of different sampling rates
    4.
    发明授权
    Method of processing digital audio signals of different sampling rates 失效
    处理不同采样率的数字音频信号的方法

    公开(公告)号：US5570308A

    公开(公告)日：1996-10-29

    申请号：US360016

    申请日：1994-12-20

    申请人： Keiichi Ochi

    发明人： Keiichi Ochi

    IPC分类号： G10L19/00 ,  G06F17/00 ,  G11B20/10 ,  H03H17/00 ,  H03H17/02

    CPC分类号： G11B20/10527

    摘要： A method of processing input digital audio signals of different sampling rates, includes steps of: providing a digital filter circuit having a random access memory (RAM) for storing input digital audio signals of different sampling rates for each of channels, a read only memory (ROM) for storing groups of digital filter coefficients, and an accumulator for executing multiplications and additions based on the input digital audio signals and the digital filter coefficients; reading the input digital audio signals of each sampling rate from the RAM; reading the digital filter coefficients of each group from the ROM; sequentially allocating one of divided time portions of one cycle of a unified sampling rate to the digital filter circuit, so that the accumulator executes the multiplications and additions for each channel during the allocated time portion so as to produce processed digital audio signals for all the channels within the one cycle; and outputting the processed digital audio signals for each of the channels at the unified sampling rate.

    摘要翻译： 一种处理不同采样率的输入数字音频信号的方法，包括以下步骤：提供具有随机存取存储器（RAM）的数字滤波器电路，用于存储每个信道的不同采样率的输入数字音频信号，只读存储器 ROM），用于存储数字滤波器系数组;以及累加器，用于基于输入的数字音频信号和数字滤波器系数执行乘法和相加; 从RAM读取每个采样率的输入数字音频信号; 从ROM读取每组的数字滤波器系数; 将统一采样率的一个周期的划分的时间部分中的一个顺序地分配给数字滤波器电路，使得累加器在分配的时间部分期间对每个信道执行乘法和加法，以便产生用于所有信道的经处理的数字音频信号 在一个周期内 并以统一的采样率输出每个信道的经处理的数字音频信号。

    Information processing device
    5.
    发明授权
    Information processing device 失效
    信息处理装置

    公开(公告)号：US5091910A

    公开(公告)日：1992-02-25

    申请号：US464387

    申请日：1990-01-12

    申请人： Keiichi Ochi

    发明人： Keiichi Ochi

    IPC分类号： G06F12/14 ,  G06F11/10 ,  G06F21/24 ,  G07F7/10 ,  G11C29/00 ,  G11C29/12 ,  G11C29/20 ,  G11C29/32 ,  G11C29/40 ,  G11C29/56

    CPC分类号： G06F11/1004 ,  G07F7/1016 ,  G11C29/12 ,  G11C29/20 ,  G11C29/32 ,  G11C29/40

    摘要： An information processing device includes a random access memory storing parallel program data, a counter generating a first address supplied to the random access memory and a second address, and a selector for converting the parallel program data read out from the random access memory in accordance with the first address into serial program data when the second address generated by the address generator is applied to the counter. Further, the information processing device includes a circuit for converting the serial program data into a cyclic code signal and outputting the cyclic code signal to an external device in which the cyclic code signal is compared with a reference cyclic signal formed on the basis of correct program data corresponding to the program data stored in the random access memory.

    摘要翻译： 信息处理装置包括存储并行程序数据的随机存取存储器，产生提供给随机存取存储器的第一地址的计数器和第二地址，以及用于根据随机存取存储器读出的并行程序数据转换的选择器 将地址生成器生成的第二个地址应用于计数器时，将第一个地址转换为串行程序数据。 此外，信息处理装置还包括一个电路，用于将串行程序数据转换为循环码信号，并将该循环码信号与循环码信号与基于正确程序形成的参考循环信号进行比较的外部装置输出 对应于存储在随机存取存储器中的程序数据的数据。