公开(公告)号：US06438047B1

公开(公告)日：2002-08-20

申请号：US09908192

申请日：2001-07-18

申请人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

发明人： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

IPC分类号： G11C700

CPC分类号： G11C29/846

摘要： A semiconductor memory device comprises a memory cell array, at least one redundant cell control, a sense amplifier, and at least one redundant cell. The memory cell array receives and outputs data through data I/O line groups. The redundant cell control stores a defective cell address, generates a redundant cell enable control signal when the defective cell address is equal to an input cell address, generates a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generates a redundant cell write control signal during a write operation in response to the redundant cell enable control signal. The sense amplifier is connected to an I/O line group commonly connected to the data I/O line groups, amplifies and outputs data outputted from the memory cell array during the read operation, and is disabled in response to the redundant cell read control signal. The redundant cell stores input data transferred to the I/O line group in response to the redundant cell write control signal and outputs stored data in response to the redundant cell read control signal.

摘要翻译： 半导体存储器件包括存储单元阵列，至少一个冗余单元控制，读出放大器和至少一个冗余单元。 存储单元阵列通过数据I / O线组接收和输出数据。 冗余单元控制存储故障单元地址，当缺陷单元地址等于输入单元地址时产生冗余单元使能控制信号，在读操作期间响应冗余单元使能控制信号产生冗余单元读控制信号 并且响应于冗余单元使能控制信号在写操作期间产生冗余单元写入控制信号。 感测放大器连接到通常连接到数据I / O线组的I / O线组，在读操作期间放大并输出从存储单元阵列输出的数据，并响应于冗余单元读取控制信号而被禁止 。 冗余单元响应于冗余单元写入控制信号存储传送到I / O线组的输入数据，并根据冗余单元读取控制信号输出存储的数据。

公开(公告)号：US06473325B2

公开(公告)日：2002-10-29

申请号：US09882209

申请日：2001-06-15

申请人： Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

发明人： Yun-Sang Lee ,  Sang-Suk Kang ,  Jae-Hoon Joo ,  Jong-Eon Lee

IPC分类号： G11C506

CPC分类号： G11C7/065 ,  G11C11/4074 ,  G11C11/4091

摘要： A layout of a bit line sensing control circuit for a semiconductor memory device includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and is connected to an active area surrounded by the power gate through the power contact.

摘要翻译： 半导体存储器件的位线检测控制电路的布局包括沿第一方向延伸的两个位线对。 电源触点设置在两个位线对之间。 电源端口设置在电源触点周围。 多个感测晶体管分别具有多个感测晶体管栅极。 多个感测晶体管栅极布置在功率门周围。 一对控制线触点在两个位线对之外的相邻位置处沿第二方向布置。 控制线在第二方向上延伸并且通过一对控制线触点连接到电源门。 电力线在与控制线相邻的第二方向上延伸，并且通过电力接触连接到被电力门围绕的有效区域。

公开(公告)号：US4920066A

公开(公告)日：1990-04-24

申请号：US292106

申请日：1988-12-30

申请人： Pil-Young Hong ,  Tae-Yup Oh ,  Chun-Joong Kim ,  Sang-Suk Kang

发明人： Pil-Young Hong ,  Tae-Yup Oh ,  Chun-Joong Kim ,  Sang-Suk Kang

IPC分类号： H01L27/10 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/823814 ,  H01L27/0927

摘要： A process for fabricating a high-speed CMOS TTL semiconductor device, wherein the operational speed of a semiconductor device is controlled by adjusting the capacitance of its field region. The capacitance of the field region is adjusted by the thickness thereof, which is determined by the control of diffusion heating cycles in the fabrication sequence according to the invention.

摘要翻译： 一种用于制造高速CMOS TTL半导体器件的工艺，其中通过调节其场区域的电容来控制半导体器件的操作速度。 通过根据本发明的制造顺序中的扩散加热循环的控制来确定场区域的电容的厚度。