公开(公告)号：US5761718A

公开(公告)日：1998-06-02

申请号：US705738

申请日：1996-08-30

Applicant: Yung Cheng Lin ,  Shih Jen Chuang

Inventor： Yung Cheng Lin ,  Shih Jen Chuang

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F2212/6026

Abstract: An algorithm for conditionally pre-fetching data for DRAM access is disclosed. A similar pattern of performing successive block reads of DRAM data in the execution of several types of instructions in a computer system is determined by analyzing CPU signals. These instructions repeatedly read blocks of data from a local memory area. Additional writes to memory or an input/output port may intervene between the repeated block reads. By using the pattern as a condition for pre-fetching data from DRAM into a high speed memory buffer of a memory controller, consecutive memory reads can be completed with zero wait state. The penalty incurred by unconditional pre-fetching of DRAM data is minimized. The conditional pre-fetching mechanism is applicable to other computer peripheral devices.

Abstract translation: 公开了一种用于有条件地预取DRAM访问数据的算法。 通过分析CPU信号来确定执行计算机系统中的几种类型的指令的DRAM数据的连续块读取的类似模式。 这些指令重复从本地存储区读取数据块。 对存储器或输入/输出端口的额外写入可能会在重复的块读取之间进行干预。 通过使用该模式作为将数据从DRAM预取到存储器控制器的高速存储器缓冲器的条件，可以以零等待状态完成连续存储器读取。 无条件预取DRAM数据造成的惩罚最小化。 条件预取机制适用于其他计算机外围设备。