公开(公告)号：US20080055220A1

公开(公告)日：2008-03-06

申请号：US11841879

申请日：2007-08-20

申请人： Yuri AZUMA ,  Yasuyuki KUDO ,  Tatsuya ISHII

发明人： Yuri AZUMA ,  Yasuyuki KUDO ,  Tatsuya ISHII

IPC分类号： G09G3/36

CPC分类号： G09G3/2096 ,  G06F3/1431 ,  G09G5/363 ,  G09G5/393 ,  G09G2320/0666 ,  G09G2340/0464 ,  G09G2340/145 ,  G09G2360/18

摘要： Tone modification of pixel data is performed, minimizing dummy cycles inserted by a host device that transfers the pixel data. A modification circuit capable of modifying tone values of pixel data sequentially transferred from an external entity comprises a shift circuit for shifting pixel data in sync with an operational clock, a parallel latch circuit for latching in parallel shift outputs for a plurality of serial pixels of pixel data passing through the shift circuit, an arithmetic circuit for arithmetic processing using the pixel data for the serial pixels latched in the parallel latch circuit, while synchronizing with shift actions of the shift circuit, and modifying an intermediate shift output of the shift circuit, and a selector that selects output of the last shift stage of the shift circuit instead of output of the arithmetic circuit for a period when a result of modification is obtained by the modification circuit, using the pixel data latched in the parallel latch circuit for pixels not placed on a same line in a transfer direction depending on the display size.

摘要翻译： 执行像素数据的色调修改，最小化由传送像素数据的主机设备插入的虚拟周期。 能够修改从外部实体顺序传送的像素数据的色调值的修正电路包括一个与运算时钟同步地移位像素数据的移位电路，用于锁存多个象素串行像素的并行移位输出的并行锁存电路 通过移位电路的数据，用于在与并行锁存电路中锁存的串行像素的像素数据进行运算处理的算术电路，同时与移位电路的移位动作同步，以及修改移位电路的中间移位输出，以及 选择器，在通过修改电路获得修正结果的期间，使用锁存在并行锁存电路中的像素未被放置的像素，选择移位电路的最后一个移位级的输出而不是运算电路的输出 根据显示尺寸在传输方向上的同一行上。

公开(公告)号：US20110153897A1

公开(公告)日：2011-06-23

申请号：US13038237

申请日：2011-03-01

申请人： Goro SAKAMAKI ,  Yuri AZUMA

发明人： Goro SAKAMAKI ,  Yuri AZUMA

IPC分类号： G06F13/14

CPC分类号： G09G5/39 ,  G06F7/768 ,  G06F9/4806 ,  G06F13/10 ,  G06F13/102 ,  G06F13/20 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4063 ,  G06F13/4221 ,  G09G3/2096 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3674 ,  G09G2310/08 ,  G09G2360/10

摘要： The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

摘要翻译： 本发明是提供一种半导体装置，即使在外部不识别到并行接口的端面，也能够正确地切换外部的端子。 半导体器件包括开关电路和第一寄存器。 开关电路是否将与外部的并行接口用作大端或小端。 第一寄存器保存开关电路的控制数据。 当第一预定控制信息（即使其高位和低位比特位置被转置时在特定比特位置的值不变）的第一预定控制信息被提供给第一寄存器时，切换电路将并行接口视为小端，并且 将并行接口视为大端，即使第二预定控制信息（即使其高位和低位比特位置被转置也在特定比特位置的值不变）被提供给第一寄存器。 无论端点设置状态如何，控制信息都可以正确输入，而不受端序设置状态的影响。

公开(公告)号：US20110068826A1

公开(公告)日：2011-03-24

申请号：US12957462

申请日：2010-12-01

申请人： Yuri AZUMA ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

发明人： Yuri AZUMA ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

IPC分类号： H03K19/0175

CPC分类号： G11C5/147

摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block.

摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路装置具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块或第二电源的指令保证第一电路块中的内部电路的操作 不能保证内部电路的运行状态。 第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有输入电路，该输入电路根据从所述第三电路块发送到所述第二电路块的控制信号 当第三电路块向第一电路块指示第二电源状态时，使得与第二电路块的工作电压保持一定的特定信号电平，而与第一电路块所提供的信号无关。