公开(公告)号：US12057810B2

公开(公告)日：2024-08-06

申请号：US18335102

申请日：2023-06-14

申请人： ZHEJIANG UNIVERSITY

发明人： Zhiwei Xu ,  Quanyong Li ,  Jiangbo Chen ,  Likang Du ,  Shengjie Wang ,  Chunyi Song

IPC分类号： H03B5/12

CPC分类号： H03B5/1212 ,  H03B2200/004 ,  H03B2200/0088

摘要： The present disclosure provides a voltage controlled oscillator for flipped and complementary low noise. The voltage controlled oscillator includes a first resonant cavity, a second resonant cavity, and an associated circuit. The associated circuit is configured to connect the first resonant cavity and the second resonant cavity in series and couple the first resonant cavity and the second resonant cavity. A resonant frequency of the first resonant cavity and a resonant frequency of the second resonant cavity satisfy a first preset condition.

公开(公告)号：US11463096B2

公开(公告)日：2022-10-04

申请号：US17489809

申请日：2021-09-30

申请人： ZHEJIANG UNIVERSITY

发明人： Zhiwei Xu ,  Jiangbo Chen ,  Jiabing Liu ,  Hui Nie ,  Kaijie Ding ,  Chunyi Song

IPC分类号： H03L7/18 ,  H03L7/089 ,  H03L7/099 ,  H04B1/40

摘要： Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

公开(公告)号：US11641207B2

公开(公告)日：2023-05-02

申请号：US17668394

申请日：2022-02-10

申请人： ZHEJIANG UNIVERSITY

发明人： Zhiwei Xu ,  Jiangbo Chen ,  Jiabing Liu ,  Hui Nie ,  Zhihao Lv ,  Chunyi Song

IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10

摘要： Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.