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公开(公告)号：US20100046269A1
公开(公告)日：2010-02-25
申请号：US12229117
申请日：2008-08-20
申请人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
摘要： An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
摘要翻译： 公开了一组存储器单元。 存储单元包括熔丝和至少一个晶体管。 晶体管用于控制保险丝的编程或感测。 将编程电压施加到第一和第二导电层的堆叠。 堆叠的第一部分将编程电压耦合到单元中的晶体管的端子。 堆叠的第二部分将编程电压耦合到另一个单元中的晶体管的端子。
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公开(公告)号：US08411482B2
公开(公告)日：2013-04-02
申请号：US12229117
申请日：2008-08-20
申请人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh Kulkarni , Kevin Zhang
摘要： A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
摘要翻译： 存储单元包括熔丝和至少一个晶体管。 晶体管用于控制保险丝的编程或感测。 将编程电压施加到第一和第二导电层的堆叠。 堆叠的第一部分将编程电压耦合到单元中的晶体管的端子。 堆叠的第二部分将编程电压耦合到另一个单元中的晶体管的端子。
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公开(公告)号：US07417913B2
公开(公告)日：2008-08-26
申请号：US11377135
申请日：2006-03-15
申请人： Zhanping Chen , Kevin Zhang
发明人： Zhanping Chen , Kevin Zhang
IPC分类号： G11C17/18
摘要： An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin. A fuse cell may include first and second fuse cells, and first and second resistance devices. The first resistance device may be configured to adjust a first voltage output from the first fuse cell, and the second resistance device may be configured to adjust a second voltage output from the second fuse cell. The first and second resistance devices may be configured adjust the first and second voltages asymmetrically.
摘要翻译： 本文公开了一种用于熔丝电池的装置，方法和系统。 在各种实施例中，熔丝单元可以包括用于调整感测余量的电路。 熔丝单元可以包括第一和第二熔丝单元，以及第一和第二电阻装置。 第一电阻装置可以被配置为调整从第一熔丝单元输出的第一电压，并且第二电阻装置可以被配置为调整从第二熔丝单元输出的第二电压。 第一和第二电阻装置可以被配置为不对称地调节第一和第二电压。
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公开(公告)号：US08395923B2
公开(公告)日：2013-03-12
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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公开(公告)号：US20080151593A1
公开(公告)日：2008-06-26
申请号：US11644381
申请日：2006-12-22
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/14 , G11C17/18 , G11C29/816
摘要： An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.
摘要翻译： 本文公开了一种用于熔丝单元阵列的装置，方法和系统。 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。
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公开(公告)号：US07924596B2
公开(公告)日：2011-04-12
申请号：US11861293
申请日：2007-09-26
申请人： Zhanping Chen , Kevin Zhang
发明人： Zhanping Chen , Kevin Zhang
IPC分类号： G11C17/00
摘要： A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.
摘要翻译： 可编程ROM（PROM）架构包括具有排列的熔丝位单元的级联NMOS晶体管，其中位于阵列的每列中的休眠晶体管在待机模式下关闭整个熔丝阵列。 熔丝冗余方案可用于修复有缺陷的熔丝排。
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公开(公告)号：US07602663B2
公开(公告)日：2009-10-13
申请号：US11644381
申请日：2006-12-22
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/14 , G11C17/18 , G11C29/816
摘要： A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.
摘要翻译： 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。
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公开(公告)号：US20090080232A1
公开(公告)日：2009-03-26
申请号：US11861293
申请日：2007-09-26
申请人： Zhanping Chen , Kevin Zhang
发明人： Zhanping Chen , Kevin Zhang
IPC分类号： G11C17/00
摘要： A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.
摘要翻译： 可编程ROM（PROM）架构包括具有排列的熔丝位单元的级联NMOS晶体管，其中位于阵列的每列中的休眠晶体管在待机模式下关闭整个熔丝阵列。 熔丝冗余方案可用于修复有缺陷的熔丝排。
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公开(公告)号：US20100165699A1
公开(公告)日：2010-07-01
申请号：US12639446
申请日：2009-12-16
申请人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
发明人： Zhanping Chen , Sarvesh H. Kulkarni , Kevin Zhang
摘要： Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
摘要翻译： 公开了用于有效实现诸如PROM，OTPROM和其它这样的可编程非易失性存储器的可编程存储器阵列电路架构的技术和电路。 电路采用反熔丝方案，其包括存储位单元阵列，每个存储器单元包含程序设备和配置有电流路径隔离阱并用于存储存储单元状态的反熔丝元件。 可以与列/行选择电路，功率选择器电路和/或读出电路结合使用的位单元配置允许高密度存储器阵列电路设计和布局。
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公开(公告)号：US20070217247A1
公开(公告)日：2007-09-20
申请号：US11377140
申请日：2006-03-15
摘要： An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality of fuse cells to asynchronously sense one or more voltages output by the plurality of fuse cells, one fuse cell at a time.
摘要翻译： 本文公开了一种用于熔丝阵列的装置，方法和系统。 在一些实施例中，熔丝阵列可以包括多个熔丝单元和耦合到多个熔丝单元的单个读出放大器以异步地感测多个熔丝单元输出的一个或多个电压，一次一个熔丝单元。
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