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公开(公告)号：US20140365156A1
公开(公告)日：2014-12-11
申请号：US13915453
申请日：2013-06-11
IPC分类号： G01K15/00
CPC分类号： G01K15/005 , G01K7/00 , G01K7/32
摘要： Embodiments of the present disclosure provide self-calibrated thermal sensors of an integrated circuit (IC) die and associated techniques and configurations. In one embodiment, a self-calibrating thermal sensing device includes a resonator configured to oscillate at a frequency corresponding with a temperature of circuitry of an integrated circuit (IC) die, wherein the resonator is thermally coupled with the circuitry and configured to operate in a first mode and a second mode and logic operatively coupled with the resonator, and configured to calculate a first temperature corresponding with a first frequency of the resonator in the first mode using a first equation, calculate a second temperature corresponding with a second frequency of the resonator in the second mode using a second equation, and add an offset to the first equation and the second equation based on a result of a comparison of the first temperature and the second temperature. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供集成电路（IC）管芯的自校准热传感器以及相关技术和配置。 在一个实施例中，自校准热感测装置包括配置成以对应于集成电路（IC）管芯的电路的温度的频率振荡的谐振器，其中谐振器与电路热耦合并且被配置为在 第一模式和第二模式以及与谐振器可操作地耦合的逻辑，并且被配置为使用第一等式计算与第一模式中的谐振器的第一频率相对应的第一温度，计算对应于谐振器的第二频率的第二温度 在第二模式中使用第二等式，并且基于第一温度和第二温度的比较的结果，向第一等式和第二等式添加偏移。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US07282937B2
公开(公告)日：2007-10-16
申请号：US10751132
申请日：2003-12-31
IPC分类号： G01R31/26
CPC分类号： G06F1/04
摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.
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3.发明授权Arrangements having IC voltage and thermal resistance designated on a per IC basis 有权具有IC电压和热阻的指令在每个IC基础上的布置公开(公告)号：US07233162B2
公开(公告)日：2007-06-19
申请号：US11182649
申请日：2005-07-14
申请人： Tawfik Arabi , Hung-Piao Ma , Gregory M. Iovino , Shai Rotem , Avner Kornfeld , Gregory F. Taylor
发明人： Tawfik Arabi , Hung-Piao Ma , Gregory M. Iovino , Shai Rotem , Avner Kornfeld , Gregory F. Taylor
IPC分类号： G01R31/26
CPC分类号： G01R31/30 , G01R31/31718 , G06F11/24
摘要： Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.
摘要翻译： 公开了用于在多个频率和电压下测试多个集成电路的系统。 在一个实施例中，多个集成电路在预定的一组频率和电压组合内至少测试一次。 如果集成电路在预定集合内的频率和电压的任何组合内失败测试，则以不同的预定组合的频率和电压重新测试集成电路。 如果集成电路在不同预定集合内的频率和电压的任何组合内进行测试失败，则集成电路被丢弃。
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公开(公告)号：US06792489B2
公开(公告)日：2004-09-14
申请号：US09823703
申请日：2001-03-30
IPC分类号： G06F1300
CPC分类号： G06F1/26
摘要： Multistage configuration and power setting for a processor includes an on-die configuration signal fuse block programmed during manufacturing, configuration signal Control and I/O circuitry, a configuration change control signal output indicating when the configuration signals are going to change, and voltage regulators and clock generators that rely on the configuration change control signal to begin the system configuration change and boot sequences. The processor actively drives its configuration signal states. Multistage configuration and power setting also enables the processor to change its configuration states during operation.
摘要翻译： 处理器的多级配置和功率设置包括在制造期间编程的管芯配置信号保险丝块，配置信号控制和I / O电路，配置变化控制信号输出，指示配置信号何时将改变，以及电压调节器和 时钟发生器依靠配置更改控制信号开始系统配置更改和引导顺序。 处理器主动驱动其配置信号状态。 多级配置和电源设置也使处理器在运行期间更改其配置状态。
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公开(公告)号：US06671847B1
公开(公告)日：2003-12-30
申请号：US09709000
申请日：2000-11-08
IPC分类号： G06F1100
CPC分类号： G11C29/1201 , G01R31/31715 , G01R31/31716
摘要： An integrated circuit includes circuitry to test input/output (I/O) devices. Test data is provided to a loopback circuit that drives data through the output buffer to the pad, and back onto the integrated circuit through the input buffer. Separate clock signals, with varying phase, are generated for input synchronous elements and output synchronous elements. The phase, and the relative time delay between the separate clocks, changes as an external clock is varied. The external clock is varied to verify the performance parameters of the I/O devices. Each I/O device includes a shift register that can be coupled to the other buffers in a chain, or can be configured to be in a loop.
摘要翻译： 集成电路包括用于测试输入/输出（I / O）设备的电路。 测试数据被提供给环回电路，其通过输出缓冲器将数据驱动到焊盘，并通过输入缓冲器返回到集成电路。 为输入同步元件和输出同步元件生成具有不同相位的独立时钟信号。 相位以及单独时钟之间的相对时间延迟随着外部时钟的变化而变化。 改变外部时钟来验证I / O设备的性能参数。 每个I / O设备包括移位寄存器，其可以耦合到链中的其他缓冲器，或者可以被配置为处于循环中。
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公开(公告)号：US5801561A
公开(公告)日：1998-09-01
申请号：US842501
申请日：1997-04-21
IPC分类号： H03K17/22
CPC分类号： H03K17/22
摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.
摘要翻译： 一种减少上电期间集成电路竞争的方法和装置。 根据本发明的一个方面，在集成电路中包括初始化电路。 响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。 替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。 响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。
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公开(公告)号：US5748033A
公开(公告)日：1998-05-05
申请号：US621652
申请日：1996-03-26
CPC分类号： G05F1/59
摘要： A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus. Based on the value of the select signal, the multiplexor generates the output voltage in response to the select signal wherein the output voltage is substantially equal to the voltage potential of the power supply line having the highest voltage potential.
摘要翻译： 一种用于产生具有多个电源的集成电路的输出电压的方法和装置。 比较器电路被耦合以从集成电路的电源总线接收电源线。 从电源总线接收的电源线具有不同的电压，这些电压可以根据具体应用而变化。 比较器比较电源线上存在的电压电位，并确定哪个电源线具有最高电位的电压。 比较器然后产生相应的选择信号，其中选择信号的值指示哪个特定的电源线具有最高的电压电位。 多路复用器被耦合以从电力总线接收选择信号以及电源线。 基于选择信号的值，多路复用器响应于选择信号产生输出电压，其中输出电压基本上等于具有最高电压电位的电源线的电压电位。
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8.发明授权Method and apparatus for implementing binary multiplication using booth type multiplication 失效使用展位类型乘法实现二进制乘法的方法和装置
公开(公告)号：US4972362A
公开(公告)日：1990-11-20
申请号：US209156
申请日：1988-06-17
CPC分类号： G06F7/5318 , G06F7/483 , G06F7/4876 , G06F7/5338 , G06F7/544 , G06F2207/3884 , G06F2207/3896 , G06F2207/5442
摘要： In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results.
摘要翻译： 在高速二进制乘法器电路中，被乘数被分割成一系列8位片，并将乘法器修改为Booth重新编码为3位组。 相应的部分乘积项在小进位存储加法器单元的规则阵列中减小。 CSA阵列的迭代使用提供了百分之七十的芯片面积或常规实现的加法器数量。 该乘法器由内部流水线驱动，由一个对用户透明的快速，两相内部时钟驱动。 内部时钟停止并在加载新的操作数和指令数据时重新启动，以将内部时钟同步到系统时钟。 本发明的其它方面包括用于指数计算的高速绝对值减法电路和浮点结果的归一化。
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公开(公告)号：US20110103170A1
公开(公告)日：2011-05-05
申请号：US12986993
申请日：2011-01-07
申请人： Jun He , Zhanping Chen , Jeffrey Hicks , Gregory F. Taylor
发明人： Jun He , Zhanping Chen , Jeffrey Hicks , Gregory F. Taylor
IPC分类号： G11C17/16
摘要： An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.
摘要翻译： 本发明的一个实施例是一种编程保险丝的技术。 编程电路产生第一和第二电流来编程保险丝。 第二电流高于第一电流。 控制电路连续地控制产生第一和第二电流。
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公开(公告)号：US07199624B2
公开(公告)日：2007-04-03
申请号：US10425914
申请日：2003-04-30
申请人： Keng L. Wong , Gregory F. Taylor , Chee How Lim
发明人： Keng L. Wong , Gregory F. Taylor , Chee How Lim
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , G06F1/10 , H03L7/087 , H03L7/235 , H03L2207/04
摘要： A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.
摘要翻译： 提供了一种系统，其包括基于参考时钟信号和反馈时钟信号输出第一信号的锁相环组件。 时钟分配网络可以基于从锁相环组件输出的第一信号来分配时钟信号。 此外，延迟锁定环路分量可能会使信号产生偏斜，并调整由时钟分配网络分配的时钟信号。
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