-
1.发明授权System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法公开(公告)号：US06873506B2
公开(公告)日：2005-03-29
申请号：US10655865
申请日：2003-09-05
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06 , H02H9/00
CPC分类号： H01L27/027 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS transistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).
摘要翻译： 本发明包括提供静电放电保护的系统和方法。 在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。 保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。 保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压 输入元件（20）。 保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。 横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。 或者，保护电路（40）还可以使用PMOS晶体管（P1）或与横向NPN晶体管（T1）组合的PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管 （T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。
搜索结果
1 条记录 (耗时 0.015 秒)
