公开(公告)号：US08435849B2

公开(公告)日：2013-05-07

申请号：US13440344

申请日：2012-04-05

Applicant: Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

Inventor： Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7847

Abstract: A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Abstract translation: 公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。 栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成 金属硅化物。 用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。 多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

公开(公告)号：US20090227084A1

公开(公告)日：2009-09-10

申请号：US12357712

申请日：2009-01-22

Applicant: Zhiqiang Wu ,  Xin Wang

Inventor： Zhiqiang Wu ,  Xin Wang

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract translation: 本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。 在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。 在第二实施例中，栅极材料是非晶态的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。 非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。 这增强了载流子迁移率并改善了晶体管驱动电流。

公开(公告)号：US20110300677A1

公开(公告)日：2011-12-08

申请号：US13209501

申请日：2011-08-15

Applicant: Zhiqiang Wu ,  Xin Wang

Inventor： Zhiqiang Wu ,  Xin Wang

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract translation: 本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。 在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。 在第二实施例中，栅极材料是非晶体的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。 非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。 这增强了载流子迁移率并改善了晶体管驱动电流。

公开(公告)号：US08048750B2

公开(公告)日：2011-11-01

申请号：US12357712

申请日：2009-01-22

Applicant: Zhiqiang Wu ,  Xin Wang

Inventor： Zhiqiang Wu ,  Xin Wang

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract translation: 本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。 在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。 在第二实施例中，栅极材料是非晶态的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。 非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。 这增强了载流子迁移率并改善了晶体管驱动电流。

公开(公告)号：US20120190158A1

公开(公告)日：2012-07-26

申请号：US13440344

申请日：2012-04-05

Applicant: Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

Inventor： Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7847

Abstract: A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Abstract translation: 公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。 栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成 金属硅化物。 用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。 多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

公开(公告)号：US08124486B2

公开(公告)日：2012-02-28

申请号：US13209501

申请日：2011-08-15

Applicant: Zhiqiang Wu ,  Xin Wang

Inventor： Zhiqiang Wu ,  Xin Wang

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract translation: 本发明提供了一种制造半导体器件的方法，该半导体器件增强了传输到沟道区的载流子迁移率增强的应力量。 在一个实施例中，在源极/漏极退火之前，在栅极电介质界面处或附近形成非晶区域。 在第二实施例中，栅极材料是非晶体的，并且处理温度保持低于栅极材料结晶温度，直到应力增强处理完成。 非晶栅极材料在高温退火期间变形，并从非晶态转变为多晶相，允许更多的应力传输到沟道区。 这增强了载流子迁移率并改善了晶体管驱动电流。

公开(公告)号：US08114727B2

公开(公告)日：2012-02-14

申请号：US12549862

申请日：2009-08-28

Applicant: Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

Inventor： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

IPC: H01L21/00

CPC classification number: H01L21/823807 ,  H01L21/823814

Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

Abstract translation: 一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。 在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。 间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。 在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。

公开(公告)号：US20110070703A1

公开(公告)日：2011-03-24

申请号：US12549862

申请日：2009-08-28

Applicant: Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

Inventor： Weize Xiong ,  Zhiqiang Wu ,  Xin Wang

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814

Abstract: An integrated process flow for forming an NMOS transistor (104) and an embedded SiGe (eSiGe) PMOS transistor (102) using a stress memorization technique (SMT) layer (126). The SMT layer (126) is deposited over both the NMOS transistor (104) and PMOS transistor (102). The portion of SMT layer (126) over PMOS transistor (102) is anisotropically etched to form spacers (128) without etching the portion of SMT layer (126) over NMOS transistor (104). Spacers (128) are used to align the SiGe recess etch and growth to form SiGe source/drain regions (132). The source/drain anneals are performed after etching the SMT layer (126) such that SMT layer (126) provides the desired stress to the NMOS transistor (104) without degrading PMOS transistor (102).

Abstract translation: 一种用于使用应力存储技术（SMT）层（126）形成NMOS晶体管（104）和嵌入式SiGe（eSiGe）PMOS晶体管（102）的集成工艺流程。 SMT层（126）沉积在NMOS晶体管（104）和PMOS晶体管（102）两者之上。 在PMOS晶体管（102）上方的SMT层（126）的部分被各向异性蚀刻以形成间隔物（128），而不通过NMOS晶体管（104）蚀刻SMT层（126）的部分。 间隔物（128）用于对准SiGe凹陷蚀刻和生长以形成SiGe源极/漏极区域（132）。 在蚀刻SMT层（126）之后执行源极/漏极退火，使得SMT层（126）在不降低PMOS晶体管（102）的情况下向NMOS晶体管（104）提供期望的应力。

公开(公告)号：USD873235S1

公开(公告)日：2020-01-21

申请号：US29672481

申请日：2018-12-06

Applicant: Xin Wang

Designer： Xin Wang

公开(公告)号：US10438069B2

公开(公告)日：2019-10-08

申请号：US15059787

申请日：2016-03-03

Applicant: Shengyin Fan ,  Zhongwei Cheng ,  Xin Wang ,  Qian Wang ,  Gang Qiao

Inventor： Shengyin Fan ,  Zhongwei Cheng ,  Xin Wang ,  Qian Wang ,  Gang Qiao

IPC: G06K9/46 ,  G06K9/62 ,  G06K9/00

Abstract: A method and an apparatus for detecting an abnormal situation are disclosed. The method includes detecting whether a first target exists in an obtained image; recognizing whether the first target holds an object, when the first target exists in the image; obtaining motion information of the object, when the first target holds the object; and determining, based on the motion information of the object, whether the abnormal situation exists.